drm/amd/display: Modify Vmin default value

Fine tune the Vmin clock value

Reviewed-by: Robin Chen <robin.chen@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Max Tseng <max.tseng@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Max Tseng 2023-09-22 16:50:53 +08:00 committed by Alex Deucher
parent 776ecb46ff
commit 3557db425d
2 changed files with 8 additions and 2 deletions

View File

@ -1914,7 +1914,7 @@ static bool dcn314_resource_construct(
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
dc->caps.color.mpc.ocsc = 1;
dc->caps.max_disp_clock_khz_at_vmin = 694000;
dc->caps.max_disp_clock_khz_at_vmin = 650000;
/* Use pipe context based otg sync logic */
dc->config.use_pipe_ctx_sync_logic = true;

View File

@ -1830,7 +1830,13 @@ static bool dcn35_resource_construct(
dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
dc->caps.color.mpc.ocsc = 1;
dc->caps.max_disp_clock_khz_at_vmin = 669154;
/* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order
* to provide some margin.
* It's expected for furture ASIC to have equal or higher value, in order to
* have determinstic power improvement from generate to genration.
* (i.e., we should not expect new ASIC generation with lower vmin rate)
*/
dc->caps.max_disp_clock_khz_at_vmin = 650000;
/* Use pipe context based otg sync logic */
dc->config.use_pipe_ctx_sync_logic = true;