ASoC: tas675x: sort the register default table

reg_defaults must be sorted by ascending register address, as
regcache_lookup_reg() locates entries in it with bsearch().  See commit
fd80df352b ("regcache: Add support for sorting defaults arrays").

TAS675X_AC_LDG_CTRL_REG (0xb5), TAS675X_TWEETER_DETECT_CTRL_REG (0xb6),
TAS675X_TWEETER_DETECT_THRESH_REG (0xb7) and TAS675X_AC_LDG_FREQ_CTRL_REG
(0xb8) are listed before the 0x7c - 0xa0 block, which leaves 14 of the
69 entries unreachable.  regcache_reg_needs_sync() then cannot compare
them against their default and reports that a sync is needed, so they
are written to the device on every regcache_sync() even when they were
never touched.

Sort the table by register address.

Fixes: 133c81f844 ("ASoC: codecs: Add TAS67524 quad-channel audio amplifier driver")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://patch.msgid.link/20260805104149.9795-6-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Peter Ujfalusi 2026-08-05 13:41:49 +03:00 committed by Mark Brown
parent e725093e9e
commit 3521d209ca
No known key found for this signature in database
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@ -1924,15 +1924,6 @@ static const struct reg_default tas675x_reg_defaults[] = {
{ TAS675X_PWM_PHASE_M_CTRL_CH2_REG, 0x00 },
{ TAS675X_PWM_PHASE_M_CTRL_CH3_REG, 0x00 },
{ TAS675X_PWM_PHASE_M_CTRL_CH4_REG, 0x00 },
{ TAS675X_DC_LDG_CTRL_REG, 0x00 },
{ TAS675X_DC_LDG_LO_CTRL_REG, 0x00 },
{ TAS675X_DC_LDG_TIME_CTRL_REG, 0x00 },
{ TAS675X_DC_LDG_SL_CH1_CH2_CTRL_REG, 0x11 },
{ TAS675X_DC_LDG_SL_CH3_CH4_CTRL_REG, 0x11 },
{ TAS675X_AC_LDG_CTRL_REG, 0x10 },
{ TAS675X_TWEETER_DETECT_CTRL_REG, 0x08 },
{ TAS675X_TWEETER_DETECT_THRESH_REG, 0x00 },
{ TAS675X_AC_LDG_FREQ_CTRL_REG, 0xC8 },
{ TAS675X_REPORT_ROUTING_1_REG, 0x00 },
{ TAS675X_OTSD_RECOVERY_EN_REG, 0x00 },
{ TAS675X_REPORT_ROUTING_2_REG, 0xA2 },
@ -1943,6 +1934,15 @@ static const struct reg_default tas675x_reg_defaults[] = {
{ TAS675X_GPIO1_OUTPUT_SEL_REG, 0x00 },
{ TAS675X_GPIO2_OUTPUT_SEL_REG, 0x00 },
{ TAS675X_GPIO_CTRL_REG, TAS675X_GPIO_CTRL_RSTVAL },
{ TAS675X_DC_LDG_CTRL_REG, 0x00 },
{ TAS675X_DC_LDG_LO_CTRL_REG, 0x00 },
{ TAS675X_DC_LDG_TIME_CTRL_REG, 0x00 },
{ TAS675X_DC_LDG_SL_CH1_CH2_CTRL_REG, 0x11 },
{ TAS675X_DC_LDG_SL_CH3_CH4_CTRL_REG, 0x11 },
{ TAS675X_AC_LDG_CTRL_REG, 0x10 },
{ TAS675X_TWEETER_DETECT_CTRL_REG, 0x08 },
{ TAS675X_TWEETER_DETECT_THRESH_REG, 0x00 },
{ TAS675X_AC_LDG_FREQ_CTRL_REG, 0xC8 },
{ TAS675X_OTW_CTRL_CH1_CH2_REG, 0x11 },
{ TAS675X_OTW_CTRL_CH3_CH4_REG, 0x11 },
};