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RK30XX/RK31XX:CONFIG_ARCH_RKXXXX replace read chip_id from ROM
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cym
parent
ab77b75794
commit
34e1e4078a
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@ -184,6 +184,7 @@ typedef uint32_t uint32;
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#define idle_req_gpu_cfg (1<<3)
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#define idle_req_video_cfg (1<<4)
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#define idle_req_vio_cfg (1<<5)
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#define idle_req_core_cfg (1<<14)
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#define idle_req_dma_cfg (1<<16)
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//PMU_PWRDN_ST
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@ -192,6 +193,7 @@ typedef uint32_t uint32;
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#define idle_gpu (1<<24)
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#define idle_video (1<<23)
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#define idle_vio (1<<22)
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#define idle_core (1<<15)
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#define idle_dma (1<<14)
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#define pd_a9_0_pwr_st (1<<0)
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@ -1021,7 +1023,6 @@ uint32_t __sramdata ddr3_tRC_tFAW[22]={
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};
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__sramdata uint32_t mem_type; // 0:LPDDR, 1:DDR, 2:DDR2, 3:DDR3, 4:LPDDR2
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__sramdata bool chip_rk3066b_flag=false;
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static __sramdata uint32_t ddr_speed_bin; // used for ddr3 only
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static __sramdata uint32_t ddr_capability_per_die; // one chip cs capability
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static __sramdata uint32_t ddr_freq;
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@ -1038,12 +1039,14 @@ static __sramdata volatile uint32_t loops_per_us;
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#define LPJ_100MHZ 999456UL
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/*static*/ void __sramlocalfunc ddr_delayus(uint32_t us)
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{
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volatile uint32_t count;
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count = loops_per_us*us;
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while(count--) // 3 cycles
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{
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do
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{
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unsigned int i = (loops_per_us*us);
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if (i < 7) i = 7;
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barrier();
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asm volatile(".align 4; 1: subs %0, %0, #1; bne 1b;" : "+r" (i));
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} while (0);
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}
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__sramfunc void ddr_copy(uint32 *pDest, uint32 *pSrc, uint32 words)
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@ -1063,20 +1066,17 @@ uint32 ddr_get_row(void)
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i = *(volatile uint32*)SysSrv_DdrConf;
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row = ddr_cfg_2_rbc[i].row;
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if(chip_rk3066b_flag == true)
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#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
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if(pGRF_Reg_RK3066B->GRF_SOC_CON[2] & (1<<1))
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{
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if(pGRF_Reg_RK3066B->GRF_SOC_CON[2] & (1<<1))
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{
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row += 1;
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}
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row += 1;
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}
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else
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#else
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if(pGRF_Reg->GRF_SOC_CON[2] & (1<<1))
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{
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if(pGRF_Reg->GRF_SOC_CON[2] & (1<<1))
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{
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row += 1;
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}
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row += 1;
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}
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#endif
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return row;
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}
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@ -2744,7 +2744,7 @@ uint32_t ddr_get_parameter(uint32_t nMHz)
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uint32_t __sramlocalfunc ddr_update_timing(void)
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{
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uint32_t i,bl_tmp;
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uint32_t i,bl_tmp=0;
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PCTL_TIMING_T *p_pctl_timing=&(ddr_reg.pctl.pctl_timing);
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PHY_TIMING_T *p_publ_timing=&(ddr_reg.publ.phy_timing);
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NOC_TIMING_T *p_noc_timing=&(ddr_reg.noc_timing);
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@ -2926,34 +2926,28 @@ __sramfunc void ddr_adjust_config(uint32_t dram_type)
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n= pCRU_Reg->CRU_PLL_CON[0][0];
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n= pPMU_Reg->PMU_WAKEUP_CFG[0];
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n= *(volatile uint32_t *)SysSrv_DdrConf;
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if(chip_rk3066b_flag == true)
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{
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n= pGRF_Reg_RK3066B->GRF_SOC_STATUS0;
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}
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else
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{
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n= pGRF_Reg->GRF_SOC_STATUS0;
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}
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#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
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n= pGRF_Reg_RK3066B->GRF_SOC_STATUS0;
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#else
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n= pGRF_Reg->GRF_SOC_STATUS0;
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#endif
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dsb();
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//enter config state
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ddr_move_to_Config_state();
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//extend capability for debug
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if(chip_rk3066b_flag == true)
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#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
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if(pGRF_Reg_RK3066B->GRF_SOC_CON[2] & (0x1<<1))
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{
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if(pGRF_Reg_RK3066B->GRF_SOC_CON[2] & (0x1<<1))
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{
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pGRF_Reg_RK3066B->GRF_SOC_CON[2] = rank_to_row15_en;
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}
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pGRF_Reg_RK3066B->GRF_SOC_CON[2] = rank_to_row15_en;
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}
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else
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#else
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if(pGRF_Reg->GRF_SOC_CON[2] & (0x1<<1))
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{
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if(pGRF_Reg->GRF_SOC_CON[2] & (0x1<<1))
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{
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pGRF_Reg->GRF_SOC_CON[2] = rank_to_row15_en;
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}
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pGRF_Reg->GRF_SOC_CON[2] = rank_to_row15_en;
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}
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#endif
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//set data training address
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pPHY_Reg->DTAR = value;
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@ -2991,15 +2985,15 @@ void __sramlocalfunc idle_port(void)
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if ( (pPMU_Reg->PMU_PWRDN_ST & pd_a9_0_pwr_st) == 0 )
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{
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#ifdef CONFIG_ARCH_RK3188
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#ifdef CONFIG_ARCH_RK3188
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pPMU_Reg->PMU_MISC_CON1 |= idle_req_dma_cfg;
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dsb();
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while( (pPMU_Reg->PMU_PWRDN_ST & idle_dma) == 0 );
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#else
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pPMU_Reg->PMU_MISC_CON1 |= idle_req_cpu_cfg;
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#else
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pPMU_Reg->PMU_MISC_CON1 |= idle_req_cup_cfg;
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dsb();
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while( (pPMU_Reg->PMU_PWRDN_ST & idle_cpu) == 0 );
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#endif
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#endif
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}
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if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st) == 0 )
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@ -3051,15 +3045,15 @@ void __sramlocalfunc deidle_port(void)
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if ( (pPMU_Reg->PMU_PWRDN_ST & pd_a9_0_pwr_st) == 0 )
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{
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#ifdef CONFIG_ARCH_RK3188
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#ifdef CONFIG_ARCH_RK3188
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pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_dma_cfg;
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dsb();
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while( (pPMU_Reg->PMU_PWRDN_ST & idle_dma) != 0 );
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#else
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#else
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pPMU_Reg->PMU_MISC_CON1 &= ~idle_req_cpu_cfg;
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dsb();
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while( (pPMU_Reg->PMU_PWRDN_ST & idle_cpu) != 0 );
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#endif
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#endif
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}
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if ( (pPMU_Reg->PMU_PWRDN_ST & pd_peri_pwr_st) == 0 )
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{
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@ -3158,38 +3152,36 @@ uint32_t __sramfunc ddr_change_freq(uint32_t nMHz)
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loops_per_us = LPJ_100MHZ*freq / 1000000;
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if(chip_rk3066b_flag == true)
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ret=ddr_set_pll_rk3600b(nMHz,0);
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else
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ret=ddr_set_pll(nMHz,0);
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#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
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ret=ddr_set_pll_rk3600b(nMHz,0);
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#else
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ret=ddr_set_pll(nMHz,0);
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#endif
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ddr_get_parameter(ret);
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/** 1. Make sure there is no host access */
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local_irq_save(flags);
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local_fiq_disable();
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local_fiq_disable();
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flush_cache_all();
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outer_flush_all();
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flush_tlb_all();
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isb();
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DDR_SAVE_SP(save_sp);
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for(i=0;i<16;i++)
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{
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n=temp[1024*i];
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barrier();
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}
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outer_flush_all();
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flush_tlb_all();
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isb();
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DDR_SAVE_SP(save_sp);
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for(i=0;i<16;i++)
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{
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n=temp[1024*i];
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barrier();
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}
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n= pDDR_Reg->SCFG.d32;
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n= pPHY_Reg->RIDR;
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n= pCRU_Reg->CRU_PLL_CON[0][0];
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n= pPMU_Reg->PMU_WAKEUP_CFG[0];
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n= *(volatile uint32_t *)SysSrv_DdrConf;
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if(chip_rk3066b_flag == true)
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{
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n= pGRF_Reg_RK3066B->GRF_SOC_STATUS0;
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}
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else
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{
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n= pGRF_Reg->GRF_SOC_STATUS0;
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}
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#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
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n= pGRF_Reg_RK3066B->GRF_SOC_STATUS0;
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#else
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n= pGRF_Reg->GRF_SOC_STATUS0;
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#endif
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dsb();
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/** 2. ddr enter self-refresh mode or precharge power-down mode */
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@ -3197,17 +3189,18 @@ uint32_t __sramfunc ddr_change_freq(uint32_t nMHz)
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ddr_selfrefresh_enter(ret);
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/** 3. change frequence */
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if(chip_rk3066b_flag == true)
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ddr_set_pll_rk3600b(ret,1);
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else
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ddr_set_pll(ret,1);
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#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
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ddr_set_pll_rk3600b(ret,1);
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#else
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ddr_set_pll(ret,1);
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#endif
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ddr_freq = ret;
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/** 5. Issues a Mode Exit command */
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ddr_selfrefresh_exit();
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deidle_port();
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dsb();
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dsb();
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DDR_RESTORE_SP(save_sp);
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local_fiq_enable();
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local_irq_restore(flags);
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@ -3244,14 +3237,11 @@ void __sramfunc ddr_suspend(void)
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n= pCRU_Reg->CRU_PLL_CON[0][0];
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n= pPMU_Reg->PMU_WAKEUP_CFG[0];
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n= *(volatile uint32_t *)SysSrv_DdrConf;
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if(chip_rk3066b_flag == true)
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{
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n= pGRF_Reg_RK3066B->GRF_SOC_STATUS0;
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}
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else
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{
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n= pGRF_Reg->GRF_SOC_STATUS0;
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}
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#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
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n= pGRF_Reg_RK3066B->GRF_SOC_STATUS0;
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#else
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n= pGRF_Reg->GRF_SOC_STATUS0;
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#endif
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dsb();
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ddr_selfrefresh_enter(0);
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@ -3277,19 +3267,16 @@ void __sramfunc ddr_resume(void)
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dsb();
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while (delay > 0)
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{
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ddr_delayus(1);
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if(chip_rk3066b_flag == true)
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{
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if (pGRF_Reg_RK3066B->GRF_SOC_STATUS0 & (0x1<<5))
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break;
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}
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else
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{
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if (pGRF_Reg->GRF_SOC_STATUS0 & (0x1<<4))
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break;
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}
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ddr_delayus(1);
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#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
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if (pGRF_Reg_RK3066B->GRF_SOC_STATUS0 & (0x1<<5))
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break;
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#else
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if (pGRF_Reg->GRF_SOC_STATUS0 & (0x1<<4))
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break;
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#endif
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delay--;
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}
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}
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pCRU_Reg->CRU_MODE_CON = (0x3<<((1*4) + 16)) | (0x1<<(1*4)); //PLL normal
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dsb();
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@ -3321,24 +3308,18 @@ uint32 ddr_get_cap(void)
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break;
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}
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row = ddr_cfg_2_rbc[i].row;
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#ifdef CONFIG_ARCH_RK3188
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if (1)
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#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
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if(pGRF_Reg_RK3066B->GRF_SOC_CON[2] & (1<<1))
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{
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row += 1;
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}
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#else
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if(*(volatile uint32_t *)(ROM_CHIP_ID_ADDR+0x0c) == 0x56313030)
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if(pGRF_Reg->GRF_SOC_CON[2] & (1<<1))
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{
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row += 1;
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}
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#endif
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{
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if(pGRF_Reg_RK3066B->GRF_SOC_CON[2] & (1<<1))
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{
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row += 1;
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}
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}
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else
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{
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if(pGRF_Reg->GRF_SOC_CON[2] & (1<<1))
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{
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row += 1;
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}
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}
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return (1 << (row+(ddr_cfg_2_rbc[i].col)+(ddr_cfg_2_rbc[i].bank)+2))*cs;
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}
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@ -3433,15 +3414,7 @@ int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
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uint32_t cs,die=1;
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uint32_t gsr,dqstr;
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ddr_print("version 1.00 20120903 \n");
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if(*(volatile uint32_t *)(ROM_CHIP_ID_ADDR+0x0c) == 0x56313030)
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{
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chip_rk3066b_flag=true;
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ddr_print("RK3066B \n");
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}
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else
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chip_rk3066b_flag=false;
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ddr_print("version 1.00 20130124 \n");
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mem_type = pPHY_Reg->DCR.b.DDRMD;
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ddr_speed_bin = dram_speed_bin;
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