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arm64: dts: rockchip: add SATA support to rk3588

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Add all three SATA IP blocks to the RK3588 DT.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20230612171337.74576-6-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Sebastian Reichel 2023-06-12 19:13:37 +02:00 committed by Heiko Stuebner
parent 6ebd55b3bb
commit 34d6c15d8e
2 changed files with 71 additions and 0 deletions
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23
arch/arm64/boot/dts/rockchip/rk3588.dtsi
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@ -129,6 +129,29 @@ gmac0_mtl_tx_setup: tx-queues-config {
};
};
sata1: sata@fe220000 {
compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
reg = <0 0xfe220000 0 0x1000>;
interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
<&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
<&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
ports-implemented = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata-port@0 {
reg = <0>;
hba-port-cap = <HBA_PORT_FBSCP>;
phys = <&combphy1_ps PHY_TYPE_SATA>;
phy-names = "sata-phy";
snps,rx-ts-max = <32>;
snps,tx-ts-max = <32>;
};
};
combphy1_ps: phy@fee10000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee10000 0x0 0x100>;

48
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
View File

@ -8,6 +8,8 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/rk3588-power.h>
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/ata/ahci.h>
/ {
compatible = "rockchip,rk3588";
@ -1180,6 +1182,52 @@ gmac1_mtl_tx_setup: tx-queues-config {
};
};
sata0: sata@fe210000 {
compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
reg = <0 0xfe210000 0 0x1000>;
interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
<&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
<&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
ports-implemented = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata-port@0 {
reg = <0>;
hba-port-cap = <HBA_PORT_FBSCP>;
phys = <&combphy0_ps PHY_TYPE_SATA>;
phy-names = "sata-phy";
snps,rx-ts-max = <32>;
snps,tx-ts-max = <32>;
};
};
sata2: sata@fe230000 {
compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
reg = <0 0xfe230000 0 0x1000>;
interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
<&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
<&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
ports-implemented = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata-port@0 {
reg = <0>;
hba-port-cap = <HBA_PORT_FBSCP>;
phys = <&combphy2_psu PHY_TYPE_SATA>;
phy-names = "sata-phy";
snps,rx-ts-max = <32>;
snps,tx-ts-max = <32>;
};
};
sdmmc: mmc@fe2c0000 {
compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe2c0000 0x0 0x4000>;