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spi: axi-spi-engine: improve version checks

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Merge series from David Lechner <dlechner@baylibre.com>:

We have a pending major version bump for the axi-spi-engine so to
prepare for that, improve the existing version checks for feature
enablement.
This commit is contained in:
Mark Brown 2025-09-12 03:25:40 +01:00
commit 34c2202f5c
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GPG Key ID: 24D68B725D5487D0
2 changed files with 28 additions and 10 deletions
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17
drivers/spi/spi-axi-spi-engine.c
View File

@ -1050,7 +1050,7 @@ static int spi_engine_probe(struct platform_device *pdev)
return -ENODEV;
}
if (ADI_AXI_PCORE_VER_MINOR(version) >= 1) {
if (adi_axi_pcore_ver_gteq(version, 1, 1)) {
unsigned int sizes = readl(spi_engine->base +
SPI_ENGINE_REG_OFFLOAD_MEM_ADDR_WIDTH);
@ -1064,7 +1064,7 @@ static int spi_engine_probe(struct platform_device *pdev)
}
/* IP v1.5 dropped the requirement for SYNC in offload messages. */
spi_engine->offload_requires_sync = ADI_AXI_PCORE_VER_MINOR(version) < 5;
spi_engine->offload_requires_sync = !adi_axi_pcore_ver_gteq(version, 1, 5);
writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_RESET);
writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
@ -1091,15 +1091,12 @@ static int spi_engine_probe(struct platform_device *pdev)
host->put_offload = spi_engine_put_offload;
host->num_chipselect = 8;
/* Some features depend of the IP core version. */
if (ADI_AXI_PCORE_VER_MAJOR(version) >= 1) {
if (ADI_AXI_PCORE_VER_MINOR(version) >= 2) {
host->mode_bits |= SPI_CS_HIGH;
host->setup = spi_engine_setup;
}
if (ADI_AXI_PCORE_VER_MINOR(version) >= 3)
host->mode_bits |= SPI_MOSI_IDLE_LOW | SPI_MOSI_IDLE_HIGH;
if (adi_axi_pcore_ver_gteq(version, 1, 2)) {
host->mode_bits |= SPI_CS_HIGH;
host->setup = spi_engine_setup;
}
if (adi_axi_pcore_ver_gteq(version, 1, 3))
host->mode_bits |= SPI_MOSI_IDLE_LOW | SPI_MOSI_IDLE_HIGH;
if (host->max_speed_hz == 0)
return dev_err_probe(&pdev->dev, -EINVAL, "spi_clk rate is 0");

21
include/linux/adi-axi-common.h
View File

@ -8,6 +8,8 @@
* https://wiki.analog.com/resources/fpga/docs/hdl/regmap
*/
#include <linux/types.h>
#ifndef ADI_AXI_COMMON_H_
#define ADI_AXI_COMMON_H_
@ -21,6 +23,25 @@
#define ADI_AXI_PCORE_VER_MINOR(version) (((version) >> 8) & 0xff)
#define ADI_AXI_PCORE_VER_PATCH(version) ((version) & 0xff)
/**
* adi_axi_pcore_ver_gteq() - check if a version is satisfied
* @version: the full version read from the hardware
* @major: the major version to compare against
* @minor: the minor version to compare against
*
* ADI AXI IP Cores use semantic versioning, so this can be used to check for
* feature availability.
*
* Return: true if the version is greater than or equal to the specified
* major and minor version, false otherwise.
*/
static inline bool adi_axi_pcore_ver_gteq(u32 version, u32 major, u32 minor)
{
return ADI_AXI_PCORE_VER_MAJOR(version) > (major) ||
(ADI_AXI_PCORE_VER_MAJOR(version) == (major) &&
ADI_AXI_PCORE_VER_MINOR(version) >= (minor));
}
#define ADI_AXI_INFO_FPGA_TECH(info) (((info) >> 24) & 0xff)
#define ADI_AXI_INFO_FPGA_FAMILY(info) (((info) >> 16) & 0xff)
#define ADI_AXI_INFO_FPGA_SPEED_GRADE(info) (((info) >> 8) & 0xff)