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clk: rockchip: rk1808: fix up the uart0 register description error

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Change-Id: I4f11f5d0a0b46557e47346064416a9ad85cdcfbd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2018-10-07 10:46:49 +08:00 committed by Tao Huang
parent d8ba58bec4
commit 34a5779682
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/rockchip/clk-rk1808.c
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@ -1084,8 +1084,8 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = {
RK1808_PMU_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS,
RK1808_PMU_CLKGATE_CON(1), 0, GFLAGS),
COMPOSITE_NOMUX_HALFDIV(0, "clk_uart0_np5", "clk_uart0_pmu_src", 0,
RK1808_CLKSEL_CON(4), 0, 7, DFLAGS,
RK1808_CLKGATE_CON(1), 1, GFLAGS),
RK1808_PMU_CLKSEL_CON(4), 0, 7, DFLAGS,
RK1808_PMU_CLKGATE_CON(1), 1, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_pmu_src", CLK_SET_RATE_PARENT,
RK1808_PMU_CLKSEL_CON(5), 0,
RK1808_PMU_CLKGATE_CON(1), 2, GFLAGS,