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PCI: rzg3s-host: Reorder reset assertion during suspend

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Reorder the reset assertion sequence during suspend from
power_resets -> cfg_resets to cfg_resets -> power_resets.
This change ensures the suspend sequence follows the reverse order
of the probe/init sequence, where power_resets are deasserted first
followed by cfg_resets.

Additionally, this ordering is required for RZ/G3E support where
cfg resets are controlled through PCIe AXI registers (offset 0x310h).
According to the RZ/G3E hardware manual (Rev.1.15, section 6.6.6.1.1
"Changing the Initial Values of the Registers"), AXI register access
requires ARESETn to be de-asserted and the clock to be supplied.
Since ARESETn is part of power_resets, cfg_resets must be asserted
before power_resets, otherwise the AXI registers become inaccessible.

Fixes: 7ef502fb35 ("PCI: Add Renesas RZ/G3S host controller driver")
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> # RZ/V2N EVK
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://patch.msgid.link/20260306143423.19562-3-john.madieu.xa@bp.renesas.com
This commit is contained in:
John Madieu 2026-03-06 15:34:09 +01:00 committed by Manivannan Sadhasivam
parent d284389d45
commit 34735f6374
1 changed files with 10 additions and 10 deletions
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20
drivers/pci/controller/pcie-rzg3s-host.c
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@ -1624,31 +1624,31 @@ static int rzg3s_pcie_suspend_noirq(struct device *dev)
clk_disable_unprepare(port->refclk);
ret = reset_control_bulk_assert(data->num_power_resets,
host->power_resets);
if (ret)
goto refclk_restore;
ret = reset_control_bulk_assert(data->num_cfg_resets,
host->cfg_resets);
if (ret)
goto power_resets_restore;
goto refclk_restore;
ret = reset_control_bulk_assert(data->num_power_resets,
host->power_resets);
if (ret)
goto cfg_resets_restore;
ret = regmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B,
RZG3S_SYS_PCIE_RST_RSM_B_MASK,
FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 0));
if (ret)
goto cfg_resets_restore;
goto power_resets_restore;
return 0;
/* Restore the previous state if any error happens */
cfg_resets_restore:
reset_control_bulk_deassert(data->num_cfg_resets,
host->cfg_resets);
power_resets_restore:
reset_control_bulk_deassert(data->num_power_resets,
host->power_resets);
cfg_resets_restore:
reset_control_bulk_deassert(data->num_cfg_resets,
host->cfg_resets);
refclk_restore:
clk_prepare_enable(port->refclk);
pm_runtime_resume_and_get(dev);