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arm64: dts: Agilex5 Add gmac nodes to DTSI for Agilex5

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Add the base device tree nodes for gmac0, gmac1, and gmac2 to the DTSI
for the Agilex5 SOCFPGA.  Agilex5 has three Ethernet controllers based on
Synopsys DWC XGMAC IP version 2.10.

Signed-off-by: Mun Yew Tham <mun.yew.tham@altera.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
This commit is contained in:
Mun Yew Tham 2025-08-18 09:39:32 -07:00 committed by Dinh Nguyen
parent 8f5ae30d69
commit 343ea11a2f
1 changed files with 336 additions and 0 deletions
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336
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
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@ -486,5 +486,341 @@ qspi: spi@108d2000 {
clocks = <&qspi_clk>;
status = "disabled";
};
gmac0: ethernet@10810000 {
compatible = "altr,socfpga-stmmac-agilex5",
"snps,dwxgmac-2.10";
reg = <0x10810000 0x3500>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
reset-names = "stmmaceth", "ahb";
clocks = <&clkmgr AGILEX5_EMAC0_CLK>,
<&clkmgr AGILEX5_EMAC_PTP_CLK>;
clock-names = "stmmaceth", "ptp_ref";
mac-address = [00 00 00 00 00 00];
tx-fifo-depth = <32768>;
rx-fifo-depth = <16384>;
snps,multicast-filter-bins = <64>;
snps,perfect-filter-entries = <64>;
snps,axi-config = <&stmmac_axi_emac0_setup>;
snps,mtl-rx-config = <&mtl_rx_emac0_setup>;
snps,mtl-tx-config = <&mtl_tx_emac0_setup>;
snps,pbl = <32>;
snps,tso;
altr,sysmgr-syscon = <&sysmgr 0x44 0>;
snps,clk-csr = <0>;
status = "disabled";
stmmac_axi_emac0_setup: stmmac-axi-config {
snps,wr_osr_lmt = <31>;
snps,rd_osr_lmt = <31>;
snps,blen = <0 0 0 32 16 8 4>;
};
mtl_rx_emac0_setup: rx-queues-config {
snps,rx-queues-to-use = <8>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x1>;
};
queue2 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x2>;
};
queue3 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x3>;
};
queue4 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x4>;
};
queue5 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x5>;
};
queue6 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x6>;
};
queue7 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x7>;
};
};
mtl_tx_emac0_setup: tx-queues-config {
snps,tx-queues-to-use = <8>;
snps,tx-sched-wrr;
queue0 {
snps,weight = <0x09>;
snps,dcb-algorithm;
};
queue1 {
snps,weight = <0x0A>;
snps,dcb-algorithm;
};
queue2 {
snps,weight = <0x0B>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue3 {
snps,weight = <0x0C>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue4 {
snps,weight = <0x0D>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue5 {
snps,weight = <0x0E>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue6 {
snps,weight = <0x0F>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue7 {
snps,weight = <0x10>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
};
};
gmac1: ethernet@10820000 {
compatible = "altr,socfpga-stmmac-agilex5",
"snps,dwxgmac-2.10";
reg = <0x10820000 0x3500>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
reset-names = "stmmaceth", "ahb";
clocks = <&clkmgr AGILEX5_EMAC1_CLK>,
<&clkmgr AGILEX5_EMAC_PTP_CLK>;
clock-names = "stmmaceth", "ptp_ref";
mac-address = [00 00 00 00 00 00];
tx-fifo-depth = <32768>;
rx-fifo-depth = <16384>;
snps,multicast-filter-bins = <64>;
snps,perfect-filter-entries = <64>;
snps,axi-config = <&stmmac_axi_emac1_setup>;
snps,mtl-rx-config = <&mtl_rx_emac1_setup>;
snps,mtl-tx-config = <&mtl_tx_emac1_setup>;
snps,pbl = <32>;
snps,tso;
altr,sysmgr-syscon = <&sysmgr 0x48 0>;
snps,clk-csr = <0>;
status = "disabled";
stmmac_axi_emac1_setup: stmmac-axi-config {
snps,wr_osr_lmt = <31>;
snps,rd_osr_lmt = <31>;
snps,blen = <0 0 0 32 16 8 4>;
};
mtl_rx_emac1_setup: rx-queues-config {
snps,rx-queues-to-use = <8>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x1>;
};
queue2 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x2>;
};
queue3 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x3>;
};
queue4 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x4>;
};
queue5 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x5>;
};
queue6 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x6>;
};
queue7 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x7>;
};
};
mtl_tx_emac1_setup: tx-queues-config {
snps,tx-queues-to-use = <8>;
snps,tx-sched-wrr;
queue0 {
snps,weight = <0x09>;
snps,dcb-algorithm;
};
queue1 {
snps,weight = <0x0A>;
snps,dcb-algorithm;
};
queue2 {
snps,weight = <0x0B>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue3 {
snps,weight = <0x0C>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue4 {
snps,weight = <0x0D>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue5 {
snps,weight = <0x0E>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue6 {
snps,weight = <0x0F>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue7 {
snps,weight = <0x10>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
};
};
gmac2: ethernet@10830000 {
compatible = "altr,socfpga-stmmac-agilex5",
"snps,dwxgmac-2.10";
reg = <0x10830000 0x3500>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
reset-names = "stmmaceth", "ahb";
clocks = <&clkmgr AGILEX5_EMAC2_CLK>,
<&clkmgr AGILEX5_EMAC_PTP_CLK>;
clock-names = "stmmaceth", "ptp_ref";
mac-address = [00 00 00 00 00 00];
tx-fifo-depth = <32768>;
rx-fifo-depth = <16384>;
snps,multicast-filter-bins = <64>;
snps,perfect-filter-entries = <64>;
snps,axi-config = <&stmmac_axi_emac2_setup>;
snps,mtl-rx-config = <&mtl_rx_emac2_setup>;
snps,mtl-tx-config = <&mtl_tx_emac2_setup>;
snps,pbl = <32>;
snps,tso;
altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
snps,clk-csr = <0>;
status = "disabled";
stmmac_axi_emac2_setup: stmmac-axi-config {
snps,wr_osr_lmt = <31>;
snps,rd_osr_lmt = <31>;
snps,blen = <0 0 0 32 16 8 4>;
};
mtl_rx_emac2_setup: rx-queues-config {
snps,rx-queues-to-use = <8>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x1>;
};
queue2 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x2>;
};
queue3 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x3>;
};
queue4 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x4>;
};
queue5 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x5>;
};
queue6 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x6>;
};
queue7 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x7>;
};
};
mtl_tx_emac2_setup: tx-queues-config {
snps,tx-queues-to-use = <8>;
snps,tx-sched-wrr;
queue0 {
snps,weight = <0x09>;
snps,dcb-algorithm;
};
queue1 {
snps,weight = <0x0A>;
snps,dcb-algorithm;
};
queue2 {
snps,weight = <0x0B>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue3 {
snps,weight = <0x0C>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue4 {
snps,weight = <0x0D>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue5 {
snps,weight = <0x0E>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue6 {
snps,weight = <0x0F>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
queue7 {
snps,weight = <0x10>;
snps,coe-unsupported;
snps,dcb-algorithm;
};
};
};
};
};