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KVM: arm64: selftest: vgic-v3: Add basic GICv3 sysreg userspace access test
We have a lot of more or less useful vgic tests, but none of them tracks the availability of GICv3 system registers, which is a bit annoying. Add one such test, which covers both EL1 and EL2 registers. Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Itaru Kitayama <itaru.kitayama@fujitsu.com> Reviewed-by: Sebastian Ott <sebott@redhat.com> Link: https://lore.kernel.org/r/20250718111154.104029-5-maz@kernel.org Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
This commit is contained in:
Marc Zyngier
Oliver Upton
parent
8af3e8ab09
commit
3435bd79ec
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@ -9,6 +9,8 @@
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#include <asm/kvm.h>
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#include <asm/kvm_para.h>
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#include <arm64/gic_v3.h>
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#include "test_util.h"
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#include "kvm_util.h"
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#include "processor.h"
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@ -18,8 +20,6 @@
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#define REG_OFFSET(vcpu, offset) (((uint64_t)vcpu << 32) | offset)
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#define GICR_TYPER 0x8
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#define VGIC_DEV_IS_V2(_d) ((_d) == KVM_DEV_TYPE_ARM_VGIC_V2)
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#define VGIC_DEV_IS_V3(_d) ((_d) == KVM_DEV_TYPE_ARM_VGIC_V3)
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@ -715,6 +715,220 @@ int test_kvm_device(uint32_t gic_dev_type)
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return 0;
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}
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struct sr_def {
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const char *name;
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u32 encoding;
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};
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#define PACK_SR(r) \
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((sys_reg_Op0(r) << 14) | \
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(sys_reg_Op1(r) << 11) | \
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(sys_reg_CRn(r) << 7) | \
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(sys_reg_CRm(r) << 3) | \
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(sys_reg_Op2(r)))
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#define SR(r) \
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{ \
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.name = #r, \
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.encoding = r, \
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}
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static const struct sr_def sysregs_el1[] = {
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SR(SYS_ICC_PMR_EL1),
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SR(SYS_ICC_BPR0_EL1),
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SR(SYS_ICC_AP0R0_EL1),
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SR(SYS_ICC_AP0R1_EL1),
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SR(SYS_ICC_AP0R2_EL1),
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SR(SYS_ICC_AP0R3_EL1),
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SR(SYS_ICC_AP1R0_EL1),
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SR(SYS_ICC_AP1R1_EL1),
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SR(SYS_ICC_AP1R2_EL1),
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SR(SYS_ICC_AP1R3_EL1),
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SR(SYS_ICC_BPR1_EL1),
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SR(SYS_ICC_CTLR_EL1),
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SR(SYS_ICC_SRE_EL1),
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SR(SYS_ICC_IGRPEN0_EL1),
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SR(SYS_ICC_IGRPEN1_EL1),
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};
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static const struct sr_def sysregs_el2[] = {
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SR(SYS_ICH_AP0R0_EL2),
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SR(SYS_ICH_AP0R1_EL2),
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SR(SYS_ICH_AP0R2_EL2),
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SR(SYS_ICH_AP0R3_EL2),
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SR(SYS_ICH_AP1R0_EL2),
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SR(SYS_ICH_AP1R1_EL2),
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SR(SYS_ICH_AP1R2_EL2),
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SR(SYS_ICH_AP1R3_EL2),
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SR(SYS_ICH_HCR_EL2),
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SR(SYS_ICC_SRE_EL2),
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SR(SYS_ICH_VTR_EL2),
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SR(SYS_ICH_VMCR_EL2),
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SR(SYS_ICH_LR0_EL2),
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SR(SYS_ICH_LR1_EL2),
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SR(SYS_ICH_LR2_EL2),
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SR(SYS_ICH_LR3_EL2),
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SR(SYS_ICH_LR4_EL2),
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SR(SYS_ICH_LR5_EL2),
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SR(SYS_ICH_LR6_EL2),
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SR(SYS_ICH_LR7_EL2),
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SR(SYS_ICH_LR8_EL2),
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SR(SYS_ICH_LR9_EL2),
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SR(SYS_ICH_LR10_EL2),
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SR(SYS_ICH_LR11_EL2),
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SR(SYS_ICH_LR12_EL2),
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SR(SYS_ICH_LR13_EL2),
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SR(SYS_ICH_LR14_EL2),
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SR(SYS_ICH_LR15_EL2),
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};
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static void test_sysreg_array(int gic, const struct sr_def *sr, int nr,
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int (*check)(int, const struct sr_def *, const char *))
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{
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for (int i = 0; i < nr; i++) {
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u64 val;
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u64 attr;
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int ret;
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/* Assume MPIDR_EL1.Aff*=0 */
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attr = PACK_SR(sr[i].encoding);
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/*
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* The API is braindead. A register can be advertised as
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* available, and yet not be readable or writable.
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* ICC_APnR{1,2,3}_EL1 are examples of such non-sense, and
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* ICH_APnR{1,2,3}_EL2 do follow suit for consistency.
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*
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* On the bright side, no known HW is implementing more than
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* 5 bits of priority, so we're safe. Sort of...
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*/
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ret = __kvm_has_device_attr(gic, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
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attr);
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TEST_ASSERT(ret == 0, "%s unavailable", sr[i].name);
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/* Check that we can write back what we read */
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ret = __kvm_device_attr_get(gic, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
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attr, &val);
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TEST_ASSERT(ret == 0 || !check(gic, &sr[i], "read"), "%s unreadable", sr[i].name);
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ret = __kvm_device_attr_set(gic, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
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attr, &val);
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TEST_ASSERT(ret == 0 || !check(gic, &sr[i], "write"), "%s unwritable", sr[i].name);
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}
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}
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static u8 get_ctlr_pribits(int gic)
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{
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int ret;
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u64 val;
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u8 pri;
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ret = __kvm_device_attr_get(gic, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
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PACK_SR(SYS_ICC_CTLR_EL1), &val);
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TEST_ASSERT(ret == 0, "ICC_CTLR_EL1 unreadable");
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pri = FIELD_GET(ICC_CTLR_EL1_PRI_BITS_MASK, val) + 1;
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TEST_ASSERT(pri >= 5 && pri <= 7, "Bad pribits %d", pri);
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return pri;
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}
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static int check_unaccessible_el1_regs(int gic, const struct sr_def *sr, const char *what)
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{
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switch (sr->encoding) {
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case SYS_ICC_AP0R1_EL1:
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case SYS_ICC_AP1R1_EL1:
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if (get_ctlr_pribits(gic) >= 6)
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return -EINVAL;
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break;
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case SYS_ICC_AP0R2_EL1:
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case SYS_ICC_AP0R3_EL1:
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case SYS_ICC_AP1R2_EL1:
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case SYS_ICC_AP1R3_EL1:
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if (get_ctlr_pribits(gic) == 7)
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return 0;
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break;
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default:
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return -EINVAL;
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}
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pr_info("SKIP %s for %s\n", sr->name, what);
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return 0;
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}
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static u8 get_vtr_pribits(int gic)
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{
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int ret;
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u64 val;
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u8 pri;
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ret = __kvm_device_attr_get(gic, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
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PACK_SR(SYS_ICH_VTR_EL2), &val);
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TEST_ASSERT(ret == 0, "ICH_VTR_EL2 unreadable");
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pri = FIELD_GET(ICH_VTR_EL2_PRIbits, val) + 1;
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TEST_ASSERT(pri >= 5 && pri <= 7, "Bad pribits %d", pri);
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return pri;
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}
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static int check_unaccessible_el2_regs(int gic, const struct sr_def *sr, const char *what)
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{
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switch (sr->encoding) {
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case SYS_ICH_AP0R1_EL2:
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case SYS_ICH_AP1R1_EL2:
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if (get_vtr_pribits(gic) >= 6)
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return -EINVAL;
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break;
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case SYS_ICH_AP0R2_EL2:
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case SYS_ICH_AP0R3_EL2:
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case SYS_ICH_AP1R2_EL2:
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case SYS_ICH_AP1R3_EL2:
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if (get_vtr_pribits(gic) == 7)
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return -EINVAL;
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break;
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default:
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return -EINVAL;
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}
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pr_info("SKIP %s for %s\n", sr->name, what);
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return 0;
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}
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static void test_v3_sysregs(void)
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{
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struct kvm_vcpu_init init = {};
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struct kvm_vcpu *vcpu;
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struct kvm_vm *vm;
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u32 feat = 0;
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int gic;
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if (kvm_check_cap(KVM_CAP_ARM_EL2))
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feat |= BIT(KVM_ARM_VCPU_HAS_EL2);
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vm = vm_create(1);
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vm_ioctl(vm, KVM_ARM_PREFERRED_TARGET, &init);
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init.features[0] |= feat;
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vcpu = aarch64_vcpu_add(vm, 0, &init, NULL);
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TEST_ASSERT(vcpu, "Can't create a vcpu?");
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gic = kvm_create_device(vm, KVM_DEV_TYPE_ARM_VGIC_V3);
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TEST_ASSERT(gic >= 0, "No GIC???");
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kvm_device_attr_set(gic, KVM_DEV_ARM_VGIC_GRP_CTRL,
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KVM_DEV_ARM_VGIC_CTRL_INIT, NULL);
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test_sysreg_array(gic, sysregs_el1, ARRAY_SIZE(sysregs_el1), check_unaccessible_el1_regs);
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if (feat)
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test_sysreg_array(gic, sysregs_el2, ARRAY_SIZE(sysregs_el2), check_unaccessible_el2_regs);
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else
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pr_info("SKIP EL2 registers, not available\n");
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close(gic);
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kvm_vm_free(vm);
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}
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void run_tests(uint32_t gic_dev_type)
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{
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test_vcpus_then_vgic(gic_dev_type);
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@ -730,6 +944,7 @@ void run_tests(uint32_t gic_dev_type)
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test_v3_last_bit_single_rdist();
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test_v3_redist_ipa_range_check_at_vcpu_run();
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test_v3_its_region();
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test_v3_sysregs();
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}
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}
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