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ASoC: mediatek: mt2701: add AFE HDMI register definitions

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Add register offsets and bit defines for the MT2701/MT7623N AFE
HDMI audio output path: the HDMI BCK divider in AUDIO_TOP_CON3,
the HDMI output memif control and descriptor registers, the 8-bit
AFE_HDMI_CONN0 interconnect, and the AFE_8CH_I2S_OUT_CON engine
that drives the HDMI TX serial link. These are a prerequisite for
adding an HDMI playback path to the mt2701 AFE driver and have no
behavioural effect on their own.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://patch.msgid.link/2c2a2e3e5d01da4a130160f5d5ffbd2a3808fe12.1776998727.git.daniel@makrotopia.org
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Daniel Golle 2026-04-24 03:49:06 +01:00 committed by Mark Brown
parent 069ac057dd
commit 3401cff9a9
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GPG Key ID: 24D68B725D5487D0
1 changed files with 29 additions and 0 deletions
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29
sound/soc/mediatek/mt2701/mt2701-reg.h
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@ -10,10 +10,17 @@
#define _MT2701_REG_H_
#define AUDIO_TOP_CON0 0x0000
#define AUDIO_TOP_CON3 0x000c
#define AUDIO_TOP_CON4 0x0010
#define AUDIO_TOP_CON5 0x0014
#define AFE_DAIBT_CON0 0x001c
#define AFE_MRGIF_CON 0x003c
#define AFE_HDMI_OUT_CON0 0x0370
#define AFE_HDMI_OUT_BASE 0x0374
#define AFE_HDMI_OUT_CUR 0x0378
#define AFE_HDMI_OUT_END 0x037c
#define AFE_HDMI_CONN0 0x0390
#define AFE_8CH_I2S_OUT_CON 0x0394
#define ASMI_TIMING_CON1 0x0100
#define ASMO_TIMING_CON1 0x0104
#define PWR1_ASM_CON1 0x0108
@ -125,6 +132,28 @@
#define AFE_MEMIF_PBUF_SIZE_DLM_BYTE_MASK (0x3 << 12)
#define AFE_MEMIF_PBUF_SIZE_DLM_32BYTES (0x1 << 12)
/* AUDIO_TOP_CON3 (0x000c) -- HDMI BCK divider */
#define AUDIO_TOP_CON3_HDMI_BCK_DIV_MASK (0x3f << 8)
#define AUDIO_TOP_CON3_HDMI_BCK_DIV(x) (((x) & 0x3f) << 8)
/* AFE_HDMI_OUT_CON0 (0x0370) */
#define AFE_HDMI_OUT_CON0_OUT_ON (0x1 << 0)
#define AFE_HDMI_OUT_CON0_BIT_WIDTH_MASK (0x1 << 1)
#define AFE_HDMI_OUT_CON0_BIT_WIDTH_16 (0x0 << 1)
#define AFE_HDMI_OUT_CON0_BIT_WIDTH_32 (0x1 << 1)
#define AFE_HDMI_OUT_CON0_CH_NUM_MASK (0xf << 4)
#define AFE_HDMI_OUT_CON0_CH_NUM(x) (((x) & 0xf) << 4)
/* AFE_8CH_I2S_OUT_CON (0x0394) -- on-SoC 8-channel I2S that feeds HDMI TX */
#define AFE_8CH_I2S_OUT_CON_EN (0x1 << 0)
#define AFE_8CH_I2S_OUT_CON_BCK_INV (0x1 << 1)
#define AFE_8CH_I2S_OUT_CON_LRCK_INV (0x1 << 2)
#define AFE_8CH_I2S_OUT_CON_I2S_DELAY (0x1 << 3)
#define AFE_8CH_I2S_OUT_CON_WLEN_MASK (0x3 << 4)
#define AFE_8CH_I2S_OUT_CON_WLEN_16BIT (0x1 << 4)
#define AFE_8CH_I2S_OUT_CON_WLEN_24BIT (0x2 << 4)
#define AFE_8CH_I2S_OUT_CON_WLEN_32BIT (0x3 << 4)
/* I2S in/out register bit control */
#define ASYS_I2S_CON_FS (0x1f << 8)
#define ASYS_I2S_CON_FS_SET(x) ((x) << 8)