From 7a0bc21b1540ca2f51c4a1806d11b1ea667e03d3 Mon Sep 17 00:00:00 2001 From: Jyothi Kumar Seerapu Date: Mon, 18 Jul 2022 20:24:22 +0530 Subject: [PATCH 1/6] pci:msm: Configure PCIe RC mode for RUMI Add PCIe RC mode support to RUMI. Change-Id: I211ac7aa4c546a2ce50d5df855112e3f90607700 Signed-off-by: Jyothi Kumar Seerapu Signed-off-by: Prudhvi Yarlagadda --- drivers/pci/controller/pci-msm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/controller/pci-msm.c b/drivers/pci/controller/pci-msm.c index 894bc63ca413..8ef03eda6b11 100644 --- a/drivers/pci/controller/pci-msm.c +++ b/drivers/pci/controller/pci-msm.c @@ -1378,6 +1378,9 @@ static void msm_pcie_rumi_init(struct msm_pcie_dev_t *pcie_dev) PCIE_DBG(pcie_dev, "PCIe: RC%d: enter.\n", pcie_dev->rc_idx); + /* configure PCIe to RC mode */ + msm_pcie_write_reg(pcie_dev->rumi, 0x54, 0x7c70); + val = readl_relaxed(pcie_dev->rumi + phy_ctrl_offs) | 0x1000; msm_pcie_write_reg(pcie_dev->rumi, phy_ctrl_offs, val); usleep_range(10000, 10001); From b802f2a6b3573dc4184aa454fc4f4d738288ea94 Mon Sep 17 00:00:00 2001 From: Prudhvi Yarlagadda Date: Mon, 25 Jul 2022 12:39:11 -0700 Subject: [PATCH 2/6] pci: msm: Add register dump for link status and control Add debug support to print the PCI_L1SS_CTL1 and PCI_EXP_LNKSTA registers during the aer interrupts. Change-Id: I487c71bc691d70972fb7ff3c7d21b667a59a8838 Signed-off-by: Prudhvi Yarlagadda --- drivers/pci/controller/pci-msm.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/pci/controller/pci-msm.c b/drivers/pci/controller/pci-msm.c index 8ef03eda6b11..5185d55e0c0c 100644 --- a/drivers/pci/controller/pci-msm.c +++ b/drivers/pci/controller/pci-msm.c @@ -692,6 +692,9 @@ struct msm_aer_err_info { unsigned int status; /* COR/UNCOR Error Status */ unsigned int mask; /* COR/UNCOR Error Mask */ struct aer_header_log_regs tlp; /* TLP Header */ + + u32 l1ss_ctl1; /* PCI_L1SS_CTL1 reg value */ + u16 lnksta; /* PCI_EXP_LNKSTA reg value */ }; struct aer_err_source { @@ -5379,6 +5382,10 @@ void msm_aer_print_error(struct pci_dev *dev, struct msm_aer_err_info *info) info->rdev->rc_idx, dev->vendor, dev->device, info->status, info->mask); + PCIE_DBG(info->rdev, "PCIe: RC%d: device [%04x:%04x] error l1ss_ctl1=%x lnkstat=%x\n", + info->rdev->rc_idx, dev->vendor, dev->device, info->l1ss_ctl1, + info->lnksta); + msm_aer_print_error_stats(dev, info); if (info->tlp_header_valid) @@ -5593,6 +5600,7 @@ static int msm_aer_get_device_error_info(struct pci_dev *dev, int type = pci_pcie_type(dev); int aer = dev->aer_cap; int temp; + u32 l1ss_cap_id_offset; /* Must reset in this function */ info->status = 0; @@ -5602,11 +5610,25 @@ static int msm_aer_get_device_error_info(struct pci_dev *dev, if (!aer) return 0; + l1ss_cap_id_offset = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS); + if (!l1ss_cap_id_offset) { + PCIE_DBG(info->rdev, + "PCIe: RC%d: Could not read l1ss cap reg offset\n", + info->rdev->rc_idx); + return 0; + } + if (info->severity == AER_CORRECTABLE) { pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &info->status); pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &info->mask); + + pci_read_config_dword(dev, l1ss_cap_id_offset + PCI_L1SS_CTL1, + &info->l1ss_ctl1); + pcie_capability_read_word(dev, PCI_EXP_LNKSTA, + &info->lnksta); + if (!(info->status & ~info->mask)) return 0; } else if (type == PCI_EXP_TYPE_ROOT_PORT || @@ -5619,6 +5641,12 @@ static int msm_aer_get_device_error_info(struct pci_dev *dev, &info->status); pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &info->mask); + + pci_read_config_dword(dev, l1ss_cap_id_offset + PCI_L1SS_CTL1, + &info->l1ss_ctl1); + pcie_capability_read_word(dev, PCI_EXP_LNKSTA, + &info->lnksta); + if (!(info->status & ~info->mask)) return 0; From 0b800d87c4cc3bb63152809e2421083adab5bc7e Mon Sep 17 00:00:00 2001 From: Jyothi Kumar Seerapu Date: Fri, 29 Jul 2022 13:02:56 +0530 Subject: [PATCH 3/6] pci: msm: Continue with probe even icc handles are missing on RUMI This change is to proceed PCIe RC probe even icc handles are not present in SDX75 RUMI validations. Currently icc changes are not mainlined and hence avoiding the issues related to icc in PCIe code. Change-Id: Ie66c62fae4e84cc68e08dfcd5a159dbdfaaebed1 Signed-off-by: Jyothi Kumar Seerapu Signed-off-by: Prudhvi Yarlagadda --- drivers/pci/controller/pci-msm.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pci-msm.c b/drivers/pci/controller/pci-msm.c index 5185d55e0c0c..1fe65d6bc980 100644 --- a/drivers/pci/controller/pci-msm.c +++ b/drivers/pci/controller/pci-msm.c @@ -4404,6 +4404,10 @@ static int msm_pcie_get_resources(struct msm_pcie_dev_t *dev, PCIE_DBG(dev, "PCIe: RC%d: entry\n", dev->rc_idx); + ret = msm_pcie_get_reg(dev); + if (ret) + return ret; + dev->icc_path = of_icc_get(&pdev->dev, "icc_path"); if (IS_ERR_OR_NULL(dev->icc_path)) { ret = dev->icc_path ? PTR_ERR(dev->icc_path) : -EINVAL; @@ -4411,7 +4415,8 @@ static int msm_pcie_get_resources(struct msm_pcie_dev_t *dev, PCIE_ERR(dev, "PCIe: RC%d: failed to get ICC path: %d\n", dev->rc_idx, ret); - return ret; + if (!dev->rumi) + return ret; } for (i = 0; i < MSM_PCIE_MAX_IRQ; i++) { @@ -4461,10 +4466,6 @@ static int msm_pcie_get_resources(struct msm_pcie_dev_t *dev, if (ret) return ret; - ret = msm_pcie_get_reg(dev); - if (ret) - return ret; - ret = msm_pcie_get_parf_status_reg(dev); if (ret) return ret; From 51dafa59bfad159757edd317e329f0dc1aed0b27 Mon Sep 17 00:00:00 2001 From: Vivek Pernamitta Date: Tue, 5 Apr 2022 17:21:34 +0530 Subject: [PATCH 4/6] msm: pci: Dump PCIe clock registers on link failure Dump PCie clocks on failure to enter link into L0, linkdown interrupt, and on receiving wake IRQ from device. Change-Id: I89430b25feeb165709ac44d3af65c73b8ab4eada Signed-off-by: Vivek Pernamitta Signed-off-by: Prudhvi Yarlagadda --- drivers/pci/controller/pci-msm.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-msm.c b/drivers/pci/controller/pci-msm.c index 1fe65d6bc980..dcac123cc362 100644 --- a/drivers/pci/controller/pci-msm.c +++ b/drivers/pci/controller/pci-msm.c @@ -35,6 +35,7 @@ #include #include #include +#include #include "../pci.h" @@ -304,7 +305,6 @@ pr_err("%s: " fmt, __func__, arg); \ } while (0) - enum msm_pcie_res { MSM_PCIE_RES_PARF, MSM_PCIE_RES_PHY, @@ -2943,6 +2943,28 @@ static bool msm_pcie_check_ltssm_state(struct msm_pcie_dev_t *dev, u32 state) return false; } +void msm_pcie_clk_dump(struct msm_pcie_dev_t *pcie_dev) +{ + struct msm_pcie_clk_info_t *clk_info; + int i; + + PCIE_ERR(pcie_dev, + "PCIe: RC%d: Dump PCIe clocks\n", + pcie_dev->rc_idx); + + clk_info = pcie_dev->clk; + for (i = 0; i < pcie_dev->num_clk; i++, clk_info++) { + if (clk_info->hdl) + qcom_clk_dump(clk_info->hdl, NULL, 0); + } + + clk_info = pcie_dev->pipe_clk; + for (i = 0; i < pcie_dev->num_pipe_clk; i++, clk_info++) { + if (clk_info->hdl) + qcom_clk_dump(clk_info->hdl, NULL, 0); + } +} + /** * msm_pcie_iatu_config - configure outbound address translation region * @dev: root commpex @@ -5772,6 +5794,7 @@ static irqreturn_t handle_wake_irq(int irq, void *data) if (dev->drv_supported && !dev->suspending && dev->link_status == MSM_PCIE_LINK_ENABLED) { + msm_pcie_clk_dump(dev); pcie_phy_dump(dev); pcie_parf_dump(dev); pcie_dm_core_dump(dev); @@ -5847,6 +5870,7 @@ static void msm_pcie_handle_linkdown(struct msm_pcie_dev_t *dev) PCIE_DUMP(dev, "PCIe:Linkdown IRQ for RC%d Dumping PCIe registers\n", dev->rc_idx); + msm_pcie_clk_dump(dev); pcie_phy_dump(dev); pcie_parf_dump(dev); pcie_dm_core_dump(dev); @@ -7165,6 +7189,7 @@ int msm_pcie_prevent_l1(struct pci_dev *pci_dev) PCIE_ERR(pcie_dev, "PCIe: RC%d: dump PCIe registers\n", pcie_dev->rc_idx); + msm_pcie_clk_dump(pcie_dev); pcie_parf_dump(pcie_dev); pcie_dm_core_dump(pcie_dev); pcie_phy_dump(pcie_dev); From 7e927d78397b8df12125c6e9e23ccc6f0555e255 Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Thu, 25 Aug 2022 23:22:35 -0700 Subject: [PATCH 5/6] pci: msm: Add support to assert/de-assert Qactive signal PCIe keeps Qactive signal asserted when link is active (L0). It de-asserts it when link is in L1SS or D3Hot. In case of L2, Qactive is not de-asserted, this prevents SNOC power collapse. Fix this issue by asserting Qactive upon link enable(L0) and de-assert it upon link disable(L2) using PCIE20_PARF_CFG_BITS_3 register. Change-Id: Iba8edb0360e6c6df9ffd1b65189fe8c92ca2c0b5 Signed-off-by: Hemant Kumar Signed-off-by: Prudhvi Yarlagadda --- drivers/pci/controller/pci-msm.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pci/controller/pci-msm.c b/drivers/pci/controller/pci-msm.c index dcac123cc362..08cdc827c35a 100644 --- a/drivers/pci/controller/pci-msm.c +++ b/drivers/pci/controller/pci-msm.c @@ -4772,6 +4772,9 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev) goto link_fail; } + /* Disable override for fal10_veto logic to de-assert Qactive signal */ + msm_pcie_write_mask(dev->parf + PCIE20_PARF_CFG_BITS_3, BIT(0), 0); + /** * configure LANE_SKEW_OFF BIT-5 and PARF_CFG_BITS_3 BIT-8 to support * dynamic link width upscaling. @@ -4898,6 +4901,10 @@ static void msm_pcie_disable(struct msm_pcie_dev_t *dev) msm_pcie_write_mask(dev->parf + PCIE20_PARF_PHY_CTRL, 0, BIT(0)); + + /* Enable override for fal10_veto logic to assert Qactive signal.*/ + msm_pcie_write_mask(dev->parf + PCIE20_PARF_CFG_BITS_3, 0, BIT(0)); + msm_pcie_clk_deinit(dev); msm_pcie_vreg_deinit(dev); msm_pcie_pipe_clk_deinit(dev); From dfb52a5eeced63ae27d86a844398091ec15ad084 Mon Sep 17 00:00:00 2001 From: Prudhvi Yarlagadda Date: Tue, 13 Sep 2022 16:16:11 -0700 Subject: [PATCH 6/6] pci: msm: Remove qcom_clk_dump calls from interrupt context qcom_clk_dump function internally has sleeping calls like mutext locks. We should not use this function in interrupt/ atomic context. Change-Id: Ic10db12ec79158ea5a532a0de5a66a2c4a49a703 Signed-off-by: Prudhvi Yarlagadda --- drivers/pci/controller/pci-msm.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pci/controller/pci-msm.c b/drivers/pci/controller/pci-msm.c index 08cdc827c35a..48459fe8444f 100644 --- a/drivers/pci/controller/pci-msm.c +++ b/drivers/pci/controller/pci-msm.c @@ -5801,7 +5801,6 @@ static irqreturn_t handle_wake_irq(int irq, void *data) if (dev->drv_supported && !dev->suspending && dev->link_status == MSM_PCIE_LINK_ENABLED) { - msm_pcie_clk_dump(dev); pcie_phy_dump(dev); pcie_parf_dump(dev); pcie_dm_core_dump(dev); @@ -5877,7 +5876,6 @@ static void msm_pcie_handle_linkdown(struct msm_pcie_dev_t *dev) PCIE_DUMP(dev, "PCIe:Linkdown IRQ for RC%d Dumping PCIe registers\n", dev->rc_idx); - msm_pcie_clk_dump(dev); pcie_phy_dump(dev); pcie_parf_dump(dev); pcie_dm_core_dump(dev);