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drm/amdgpu: retire legacy PMFW bad page loading in page

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Remove the legacy logic that loads RAS bad pages from PMFW during
page retirement

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Ce Sun <cesun102@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ce Sun 2026-06-03 16:06:23 +08:00 committed by Alex Deucher
parent fe3ede5cda
commit 33f0bfcf16
2 changed files with 57 additions and 74 deletions
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7
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
View File

@ -3045,12 +3045,7 @@ int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
mutex_lock(&con->recovery_lock);
control = &con->eeprom_control;
data = con->eh_data;
if (amdgpu_ras_smu_eeprom_supported(adev))
unit_num = control->ras_num_recs -
control->ras_num_recs_old;
else
unit_num = data->count / adev->umc.retire_unit -
control->ras_num_recs;
unit_num = data->count / adev->umc.retire_unit - control->ras_num_recs;
save_count = con->bad_page_num - control->ras_num_bad_pages;
mutex_unlock(&con->recovery_lock);

124
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
View File

@ -97,7 +97,6 @@ void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev,
{
struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct amdgpu_ras_eeprom_control *control = &con->eeprom_control;
unsigned int error_query_mode;
int ret = 0;
unsigned long err_count;
@ -118,77 +117,66 @@ void amdgpu_umc_handle_bad_pages(struct amdgpu_device *adev,
err_data->err_addr_len = adev->umc.max_ras_err_cnt_per_query;
mutex_lock(&con->page_retirement_lock);
if (!amdgpu_ras_smu_eeprom_supported(adev)) {
ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(con->umc_ecc));
if (ret == -EOPNOTSUPP &&
error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) {
if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev,
ras_error_status);
ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(con->umc_ecc));
if (ret == -EOPNOTSUPP &&
error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) {
if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev,
ras_error_status);
if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
adev->umc.ras->ras_block.hw_ops->query_ras_error_address &&
adev->umc.max_ras_err_cnt_per_query) {
kfree(err_data->err_addr);
err_data->err_addr =
kzalloc_objs(struct eeprom_table_record,
adev->umc.max_ras_err_cnt_per_query);
if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
adev->umc.ras->ras_block.hw_ops->query_ras_error_address &&
adev->umc.max_ras_err_cnt_per_query) {
err_data->err_addr =
kzalloc_objs(struct eeprom_table_record,
adev->umc.max_ras_err_cnt_per_query);
/* still call query_ras_error_address to clear error status
* even NOMEM error is encountered
*/
if (!err_data->err_addr)
dev_warn(adev->dev,
"Failed to alloc memory for umc error address record!\n");
else
err_data->err_addr_len =
adev->umc.max_ras_err_cnt_per_query;
/* still call query_ras_error_address to clear error status
* even NOMEM error is encountered
*/
if (!err_data->err_addr)
dev_warn(adev->dev,
"Failed to alloc memory for umc error address record!\n");
else
err_data->err_addr_len =
adev->umc.max_ras_err_cnt_per_query;
/* umc query_ras_error_address is also responsible for clearing
* error status
*/
adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev,
ras_error_status);
}
} else if (error_query_mode == AMDGPU_RAS_FIRMWARE_ERROR_QUERY ||
(!ret && error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY)) {
if (adev->umc.ras &&
adev->umc.ras->ecc_info_query_ras_error_count)
adev->umc.ras->ecc_info_query_ras_error_count(adev,
ras_error_status);
if (adev->umc.ras &&
adev->umc.ras->ecc_info_query_ras_error_address &&
adev->umc.max_ras_err_cnt_per_query) {
kfree(err_data->err_addr);
err_data->err_addr =
kzalloc_objs(struct eeprom_table_record,
adev->umc.max_ras_err_cnt_per_query);
/* still call query_ras_error_address to clear error status
* even NOMEM error is encountered
*/
if (!err_data->err_addr)
dev_warn(adev->dev,
"Failed to alloc memory for umc error address record!\n");
else
err_data->err_addr_len =
adev->umc.max_ras_err_cnt_per_query;
/* umc query_ras_error_address is also responsible for clearing
* error status
*/
adev->umc.ras->ecc_info_query_ras_error_address(adev,
ras_error_status);
}
/* umc query_ras_error_address is also responsible for clearing
* error status
*/
adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev,
ras_error_status);
}
} else {
if (!amdgpu_ras_eeprom_update_record_num(control)) {
err_data->err_addr_cnt = err_data->de_count =
control->ras_num_recs - control->ras_num_recs_old;
amdgpu_ras_eeprom_read_idx(control, err_data->err_addr,
control->ras_num_recs_old, err_data->de_count);
} else if (error_query_mode == AMDGPU_RAS_FIRMWARE_ERROR_QUERY ||
(!ret && error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY)) {
if (adev->umc.ras &&
adev->umc.ras->ecc_info_query_ras_error_count)
adev->umc.ras->ecc_info_query_ras_error_count(adev,
ras_error_status);
if (adev->umc.ras &&
adev->umc.ras->ecc_info_query_ras_error_address &&
adev->umc.max_ras_err_cnt_per_query) {
err_data->err_addr =
kcalloc(adev->umc.max_ras_err_cnt_per_query,
sizeof(struct eeprom_table_record), GFP_KERNEL);
/* still call query_ras_error_address to clear error status
* even NOMEM error is encountered
*/
if (!err_data->err_addr)
dev_warn(adev->dev,
"Failed to alloc memory for umc error address record!\n");
else
err_data->err_addr_len =
adev->umc.max_ras_err_cnt_per_query;
/* umc query_ras_error_address is also responsible for clearing
* error status
*/
adev->umc.ras->ecc_info_query_ras_error_address(adev,
ras_error_status);
}
}