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clk: renesas: rzg2l: Refactor rzg3l_cpg_pll_clk_endisable()

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Reduce duplication by introducing mon_mask.
Eliminate an else branch by moving common parts into variable
pre-initializations.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/9cda94b9b37c562a305f4dd6091fd71246764fd2.1777562043.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2026-04-30 17:20:18 +02:00
parent 44c1733331
commit 33cd08ac62
1 changed files with 7 additions and 9 deletions
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16
drivers/clk/renesas/rzg2l-cpg.c
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@ -1197,27 +1197,25 @@ static int rzg3l_cpg_pll_clk_endisable(struct clk_hw *hw, bool enable)
{
struct pll_clk *pll_clk = to_pll(hw);
struct rzg2l_cpg_priv *priv = pll_clk->priv;
u32 mon_mask = RZG3L_PLL_MON_RESETB | RZG3L_PLL_MON_LOCK;
u32 val = RZG3L_PLL_STBY_RESETB_WEN;
u32 stby_offset, mon_offset;
u32 val, mon_val;
u32 mon_val = 0;
int ret;
stby_offset = RZG3L_PLL_STBY_OFFSET(pll_clk->conf);
mon_offset = RZG3L_PLL_MON_OFFSET(pll_clk->conf);
if (enable) {
val = RZG3L_PLL_STBY_RESETB_WEN | RZG3L_PLL_STBY_RESETB;
mon_val = RZG3L_PLL_MON_RESETB | RZG3L_PLL_MON_LOCK;
} else {
val = RZG3L_PLL_STBY_RESETB_WEN;
mon_val = 0;
val |= RZG3L_PLL_STBY_RESETB;
mon_val = mon_mask;
}
writel(val, priv->base + stby_offset);
/* ensure PLL is in normal/standby mode */
ret = readl_poll_timeout_atomic(priv->base + mon_offset, val, mon_val ==
(val & (RZG3L_PLL_MON_RESETB | RZG3L_PLL_MON_LOCK)),
10, 100);
ret = readl_poll_timeout_atomic(priv->base + mon_offset, val,
mon_val == (val & mon_mask), 10, 100);
if (ret)
dev_err(priv->dev, "Failed to %s PLL 0x%x/%pC\n", enable ?
"enable" : "disable", stby_offset, hw->clk);