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dt-bindings: clock: Add Amlogic A9 peripherals clock controller
Add the peripherals clock controller dt-bindings for the Amlogic A9 SoC family. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Jian Hu <jian.hu@amlogic.com> Link: https://patch.msgid.link/20260701-a9_peripherals-v6-1-9630f39879e5@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This commit is contained in:
Jian Hu
Jerome Brunet
parent
a1b4c3a63a
commit
33972977d6
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2026 Amlogic, Inc. All rights reserved
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/amlogic,a9-peripherals-clkc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic A9 Series Peripherals Clock Controller
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maintainers:
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- Neil Armstrong <neil.armstrong@linaro.org>
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- Jerome Brunet <jbrunet@baylibre.com>
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- Jian Hu <jian.hu@amlogic.com>
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- Xianwei Zhao <xianwei.zhao@amlogic.com>
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properties:
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compatible:
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const: amlogic,a9-peripherals-clkc
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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clocks:
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minItems: 27
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items:
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- description: input oscillator
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- description: input fclk div 2
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- description: input fclk div 3
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- description: input fclk div 4
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- description: input fclk div 5
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- description: input fclk div 7
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- description: input fclk div 2p5
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- description: input sys clk
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- description: input gp1 pll
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- description: input gp2 pll
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- description: input sys pll div 16
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- description: input cpu clk div 16
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- description: input a78 clk div 16
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- description: input dsu clk div 16
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- description: input rtc clk
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- description: input gp0 pll
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- description: input hifi0 pll
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- description: input hifi1 pll
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- description: input mclk0 pll
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- description: input mclk1 pll
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- description: input video1 pll
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- description: input video2 pll
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- description: input hdmi out2 clk
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- description: input hdmi pixel clk
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- description: input pixel0 pll
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- description: input pixel1 pll
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- description: input ddr pll test clk
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- description: external input rmii oscillator (optional)
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clock-names:
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minItems: 27
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items:
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- const: xtal
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- const: fdiv2
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- const: fdiv3
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- const: fdiv4
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- const: fdiv5
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- const: fdiv7
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- const: fdiv2p5
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- const: sys
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- const: gp1
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- const: gp2
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- const: sysplldiv16
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- const: cpudiv16
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- const: a78div16
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- const: dsudiv16
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- const: rtc
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- const: gp0
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- const: hifi0
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- const: hifi1
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- const: mclk0
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- const: mclk1
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- const: vid1
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- const: vid2
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- const: hdmiout2
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- const: hdmipix
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- const: pix0
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- const: pix1
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- const: ddr_test
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- const: ext_rmii
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required:
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- compatible
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- reg
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- '#clock-cells'
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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clock-controller@200 {
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compatible = "amlogic,a9-peripherals-clkc";
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reg = <0x0 0x200 0x0 0x2f8>;
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#clock-cells = <1>;
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clocks = <&xtal>,
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<&scmi_clk 10>,
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<&scmi_clk 12>,
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<&scmi_clk 14>,
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<&scmi_clk 16>,
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<&scmi_clk 18>,
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<&scmi_clk 20>,
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<&scmi_clk 21>,
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<&scmi_clk 33>,
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<&scmi_clk 34>,
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<&scmi_clk 35>,
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<&scmi_clk 36>,
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<&scmi_clk 37>,
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<&scmi_clk 38>,
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<&scmi_clk 40>,
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<&gp0 3>,
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<&hifi0 3>,
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<&hifi1 3>,
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<&mclk0 3>,
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<&mclk1 3>,
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<&vid1>,
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<&vid2>,
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<&hdmitx 10>,
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<&hdmitx 11>,
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<&pix0>,
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<&pix1>,
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<&ddr 3>;
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clock-names = "xtal",
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"fdiv2",
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"fdiv3",
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"fdiv4",
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"fdiv5",
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"fdiv7",
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"fdiv2p5",
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"sys",
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"gp1",
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"gp2",
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"sysplldiv16",
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"cpudiv16",
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"a78div16",
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"dsudiv16",
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"rtc",
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"gp0",
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"hifi0",
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"hifi1",
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"mclk0",
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"mclk1",
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"vid1",
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"vid2",
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"hdmiout2",
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"hdmipix",
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"pix0",
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"pix1",
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"ddr_test";
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};
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};
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351
include/dt-bindings/clock/amlogic,a9-peripherals-clkc.h
Normal file
351
include/dt-bindings/clock/amlogic,a9-peripherals-clkc.h
Normal file
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@ -0,0 +1,351 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (C) 2026 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __AMLOGIC_A9_PERIPHERALS_CLKC_H
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#define __AMLOGIC_A9_PERIPHERALS_CLKC_H
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#define CLKID_SYS_AM_AXI 0
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#define CLKID_SYS_DOS 1
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#define CLKID_SYS_MIPI_DSI0 2
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#define CLKID_SYS_ETH_PHY 3
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#define CLKID_SYS_AMFC 4
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#define CLKID_SYS_MALI 5
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#define CLKID_SYS_NNA 6
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#define CLKID_SYS_ETH_AXI 7
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#define CLKID_SYS_DP_APB 8
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#define CLKID_SYS_EDPTX_APB 9
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#define CLKID_SYS_U3HSG 10
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#define CLKID_SYS_AUCPU 11
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#define CLKID_SYS_GLB 12
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#define CLKID_SYS_COMBO_DPHY_APB 13
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#define CLKID_SYS_HDMIRX_APB 14
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#define CLKID_SYS_HDMIRX_PCLK 15
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#define CLKID_SYS_MIPI_DSI0_PHY 16
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#define CLKID_SYS_CAN0 17
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#define CLKID_SYS_CAN1 18
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#define CLKID_SYS_SD_EMMC_A 19
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#define CLKID_SYS_SD_EMMC_B 20
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#define CLKID_SYS_SD_EMMC_C 21
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#define CLKID_SYS_SC 22
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#define CLKID_SYS_ACODEC 23
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#define CLKID_SYS_MIPI_ISP 24
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#define CLKID_SYS_MSR 25
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#define CLKID_SYS_AUDIO 26
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#define CLKID_SYS_MIPI_DSI1 27
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#define CLKID_SYS_MIPI_DSI1_PHY 28
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#define CLKID_SYS_ETH 29
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#define CLKID_SYS_ETH_1G_MAC 30
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#define CLKID_SYS_UART_A 31
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#define CLKID_SYS_UART_F 32
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#define CLKID_SYS_TS_A55 33
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#define CLKID_SYS_ETH_1G_AXI 34
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#define CLKID_SYS_TS_DOS 35
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#define CLKID_SYS_U3DRD_B 36
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#define CLKID_SYS_TS_CORE 37
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#define CLKID_SYS_TS_PLL 38
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#define CLKID_SYS_CSI_DIG_CLKIN 39
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#define CLKID_SYS_CVE 40
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#define CLKID_SYS_GE2D 41
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#define CLKID_SYS_SPISG 42
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#define CLKID_SYS_U2H 43
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#define CLKID_SYS_PCIE_MAC_A 44
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#define CLKID_SYS_U3DRD_A 45
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#define CLKID_SYS_U2DRD 46
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#define CLKID_SYS_PCIE_PHY 47
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#define CLKID_SYS_PCIE_MAC_B 48
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#define CLKID_SYS_PERIPH 49
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#define CLKID_SYS_PIO 50
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#define CLKID_SYS_I3C 51
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#define CLKID_SYS_I2C_M_E 52
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#define CLKID_SYS_I2C_M_F 53
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#define CLKID_SYS_HDMITX_APB 54
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#define CLKID_SYS_I2C_M_I 55
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#define CLKID_SYS_I2C_M_G 56
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#define CLKID_SYS_I2C_M_H 57
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#define CLKID_SYS_HDMI20_AES 58
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#define CLKID_SYS_CSI2_HOST 59
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#define CLKID_SYS_CSI2_ADAPT 60
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#define CLKID_SYS_DSPA 61
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#define CLKID_SYS_PP_DMA 62
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#define CLKID_SYS_PP_WRAPPER 63
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#define CLKID_SYS_VPU_INTR 64
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#define CLKID_SYS_CSI2_PHY 65
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#define CLKID_SYS_SARADC 66
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#define CLKID_SYS_PWM_J 67
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#define CLKID_SYS_PWM_I 68
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#define CLKID_SYS_PWM_H 69
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#define CLKID_SYS_PWM_N 70
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#define CLKID_SYS_PWM_M 71
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#define CLKID_SYS_PWM_L 72
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#define CLKID_SYS_PWM_K 73
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#define CLKID_SD_EMMC_A_SEL 74
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#define CLKID_SD_EMMC_A_DIV 75
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#define CLKID_SD_EMMC_A 76
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#define CLKID_SD_EMMC_B_SEL 77
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#define CLKID_SD_EMMC_B_DIV 78
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#define CLKID_SD_EMMC_B 79
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#define CLKID_SD_EMMC_C_SEL 80
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#define CLKID_SD_EMMC_C_DIV 81
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#define CLKID_SD_EMMC_C 82
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#define CLKID_PWM_H_SEL 83
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#define CLKID_PWM_H_DIV 84
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#define CLKID_PWM_H 85
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#define CLKID_PWM_I_SEL 86
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#define CLKID_PWM_I_DIV 87
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#define CLKID_PWM_I 88
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#define CLKID_PWM_J_SEL 89
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#define CLKID_PWM_J_DIV 90
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#define CLKID_PWM_J 91
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#define CLKID_PWM_K_SEL 92
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#define CLKID_PWM_K_DIV 93
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#define CLKID_PWM_K 94
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#define CLKID_PWM_L_SEL 95
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#define CLKID_PWM_L_DIV 96
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#define CLKID_PWM_L 97
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#define CLKID_PWM_M_SEL 98
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#define CLKID_PWM_M_DIV 99
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#define CLKID_PWM_M 100
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#define CLKID_PWM_N_SEL 101
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#define CLKID_PWM_N_DIV 102
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#define CLKID_PWM_N 103
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#define CLKID_SPISG0_SEL 104
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#define CLKID_SPISG0_DIV 105
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#define CLKID_SPISG0 106
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#define CLKID_SPISG1_SEL 107
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#define CLKID_SPISG1_DIV 108
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#define CLKID_SPISG1 109
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#define CLKID_SPISG2_SEL 110
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#define CLKID_SPISG2_DIV 111
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#define CLKID_SPISG2 112
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#define CLKID_SARADC_SEL 113
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#define CLKID_SARADC_DIV 114
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#define CLKID_SARADC 115
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#define CLKID_AMFC_SEL 116
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#define CLKID_AMFC_DIV 117
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#define CLKID_AMFC 118
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#define CLKID_NNA_SEL 119
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#define CLKID_NNA_DIV 120
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#define CLKID_NNA 121
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#define CLKID_USB_250M_SEL 122
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#define CLKID_USB_250M_DIV 123
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#define CLKID_USB_250M 124
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#define CLKID_USB_48M_PRE_SEL 125
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#define CLKID_USB_48M_PRE_DIV 126
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#define CLKID_USB_48M_PRE 127
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#define CLKID_PCIE0_TL_SEL 128
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#define CLKID_PCIE0_TL_DIV 129
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#define CLKID_PCIE0_TL 130
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#define CLKID_PCIE1_TL_SEL 131
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#define CLKID_PCIE1_TL_DIV 132
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#define CLKID_PCIE1_TL 133
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#define CLKID_CMPR_SEL 134
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#define CLKID_CMPR_DIV 135
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#define CLKID_CMPR 136
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#define CLKID_DEWARPA_SEL 137
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#define CLKID_DEWARPA_DIV 138
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#define CLKID_DEWARPA 139
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#define CLKID_SC_PRE_SEL 140
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#define CLKID_SC_PRE_DIV 141
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#define CLKID_SC_PRE 142
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#define CLKID_SC 143
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#define CLKID_DPTX_APB2_SEL 144
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#define CLKID_DPTX_APB2_DIV 145
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#define CLKID_DPTX_APB2 146
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#define CLKID_DPTX_AUD_SEL 147
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#define CLKID_DPTX_AUD_DIV 148
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#define CLKID_DPTX_AUD 149
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#define CLKID_ISP_SEL 150
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#define CLKID_ISP_DIV 151
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#define CLKID_ISP 152
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#define CLKID_CVE_SEL 153
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#define CLKID_CVE_DIV 154
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#define CLKID_CVE 155
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#define CLKID_VGE_SEL 156
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#define CLKID_VGE_DIV 157
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#define CLKID_VGE 158
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#define CLKID_PP_SEL 159
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#define CLKID_PP_DIV 160
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#define CLKID_PP 161
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#define CLKID_GLB_SEL 162
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#define CLKID_GLB_DIV 163
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#define CLKID_GLB 164
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#define CLKID_USB_48M_DUALDIV_IN 165
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#define CLKID_USB_48M_DUALDIV_DIV 166
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#define CLKID_USB_48M_DUALDIV_SEL 167
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#define CLKID_USB_48M_DUALDIV 168
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#define CLKID_USB_48M 169
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#define CLKID_CAN0_PE_SEL 170
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#define CLKID_CAN0_PE_DIV 171
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#define CLKID_CAN0_PE 172
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#define CLKID_CAN1_PE_SEL 173
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#define CLKID_CAN1_PE_DIV 174
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#define CLKID_CAN1_PE 175
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#define CLKID_CAN0_FILTER_SEL 176
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#define CLKID_CAN0_FILTER_DIV 177
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#define CLKID_CAN0_FILTER 178
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#define CLKID_CAN1_FILTER_SEL 179
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#define CLKID_CAN1_FILTER_DIV 180
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#define CLKID_CAN1_FILTER 181
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#define CLKID_I3C_SEL 182
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#define CLKID_I3C_DIV 183
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#define CLKID_I3C 184
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#define CLKID_TS_DIV 185
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#define CLKID_TS 186
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#define CLKID_ETH_125M_DIV 187
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#define CLKID_ETH_125M 188
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#define CLKID_ETH_RMII_SEL 189
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#define CLKID_ETH_RMII_DIV 190
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#define CLKID_ETH_RMII 191
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#define CLKID_GEN_SEL 192
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#define CLKID_GEN_DIV 193
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#define CLKID_GEN 194
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#define CLKID_CLK24M_IN 195
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#define CLKID_CLK12_24M 196
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#define CLKID_MALI_0_SEL 197
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#define CLKID_MALI_0_DIV 198
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#define CLKID_MALI_0 199
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#define CLKID_MALI_1_SEL 200
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#define CLKID_MALI_1_DIV 201
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#define CLKID_MALI_1 202
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#define CLKID_MALI 203
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#define CLKID_MALI_STACK_0_SEL 204
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#define CLKID_MALI_STACK_0_DIV 205
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#define CLKID_MALI_STACK_0 206
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#define CLKID_MALI_STACK_1_SEL 207
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#define CLKID_MALI_STACK_1_DIV 208
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#define CLKID_MALI_STACK_1 209
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#define CLKID_MALI_STACK 210
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#define CLKID_DSPA_0_SEL 211
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#define CLKID_DSPA_0_DIV 212
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#define CLKID_DSPA_0 213
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#define CLKID_DSPA_1_SEL 214
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#define CLKID_DSPA_1_DIV 215
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#define CLKID_DSPA_1 216
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#define CLKID_DSPA 217
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#define CLKID_HEVCF_0_SEL 218
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#define CLKID_HEVCF_0_DIV 219
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#define CLKID_HEVCF_0 220
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#define CLKID_HEVCF_1_SEL 221
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#define CLKID_HEVCF_1_DIV 222
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#define CLKID_HEVCF_1 223
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#define CLKID_HEVCF 224
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#define CLKID_HCODEC_0_SEL 225
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#define CLKID_HCODEC_0_DIV 226
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#define CLKID_HCODEC_0 227
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#define CLKID_HCODEC_1_SEL 228
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#define CLKID_HCODEC_1_DIV 229
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#define CLKID_HCODEC_1 230
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#define CLKID_HCODEC 231
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#define CLKID_VPU_0_SEL 232
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#define CLKID_VPU_0_DIV 233
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#define CLKID_VPU_0 234
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#define CLKID_VPU_1_SEL 235
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#define CLKID_VPU_1_DIV 236
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#define CLKID_VPU_1 237
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#define CLKID_VPU 238
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#define CLKID_VAPB_0_SEL 239
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#define CLKID_VAPB_0_DIV 240
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#define CLKID_VAPB_0 241
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#define CLKID_VAPB_1_SEL 242
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#define CLKID_VAPB_1_DIV 243
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#define CLKID_VAPB_1 244
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#define CLKID_VAPB 245
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#define CLKID_GE2D 246
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#define CLKID_VPU_CLKB_TMP_SEL 247
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#define CLKID_VPU_CLKB_TMP_DIV 248
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#define CLKID_VPU_CLKB_TMP 249
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#define CLKID_VPU_CLKB_DIV 250
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||||
#define CLKID_VPU_CLKB 251
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#define CLKID_HDMITX_SYS_SEL 252
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#define CLKID_HDMITX_SYS_DIV 253
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#define CLKID_HDMITX_SYS 254
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#define CLKID_HDMITX_PRIF_SEL 255
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#define CLKID_HDMITX_PRIF_DIV 256
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#define CLKID_HDMITX_PRIF 257
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#define CLKID_HDMITX_200M_SEL 258
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#define CLKID_HDMITX_200M_DIV 259
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#define CLKID_HDMITX_200M 260
|
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#define CLKID_HDMITX_AUD_SEL 261
|
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#define CLKID_HDMITX_AUD_DIV 262
|
||||
#define CLKID_HDMITX_AUD 263
|
||||
#define CLKID_HDMIRX_5M_SEL 264
|
||||
#define CLKID_HDMIRX_5M_DIV 265
|
||||
#define CLKID_HDMIRX_5M 266
|
||||
#define CLKID_HDMIRX_2M_SEL 267
|
||||
#define CLKID_HDMIRX_2M_DIV 268
|
||||
#define CLKID_HDMIRX_2M 269
|
||||
#define CLKID_HDMIRX_CFG_SEL 270
|
||||
#define CLKID_HDMIRX_CFG_DIV 271
|
||||
#define CLKID_HDMIRX_CFG 272
|
||||
#define CLKID_HDMIRX_HDCP2X_SEL 273
|
||||
#define CLKID_HDMIRX_HDCP2X_DIV 274
|
||||
#define CLKID_HDMIRX_HDCP2X 275
|
||||
#define CLKID_HDMIRX_ACR_REF_SEL 276
|
||||
#define CLKID_HDMIRX_ACR_REF_DIV 277
|
||||
#define CLKID_HDMIRX_ACR_REF 278
|
||||
#define CLKID_HDMIRX_METER_SEL 279
|
||||
#define CLKID_HDMIRX_METER_DIV 280
|
||||
#define CLKID_HDMIRX_METER 281
|
||||
#define CLKID_VID_LOCK_SEL 282
|
||||
#define CLKID_VID_LOCK_DIV 283
|
||||
#define CLKID_VID_LOCK 284
|
||||
#define CLKID_VDIN_MEAS_SEL 285
|
||||
#define CLKID_VDIN_MEAS_DIV 286
|
||||
#define CLKID_VDIN_MEAS 287
|
||||
#define CLKID_VID_PLL_DIV 288
|
||||
#define CLKID_VID_PLL_SEL 289
|
||||
#define CLKID_VID_PLL 290
|
||||
#define CLKID_VID_PLL_VCLK 291
|
||||
#define CLKID_VCLK0_SEL 292
|
||||
#define CLKID_VCLK0_IN 293
|
||||
#define CLKID_VCLK0_DIV 294
|
||||
#define CLKID_VCLK0 295
|
||||
#define CLKID_VCLK0_DIV1_EN 296
|
||||
#define CLKID_VCLK0_DIV2_EN 297
|
||||
#define CLKID_VCLK0_DIV2 298
|
||||
#define CLKID_VCLK0_DIV4_EN 299
|
||||
#define CLKID_VCLK0_DIV4 300
|
||||
#define CLKID_VCLK0_DIV6_EN 301
|
||||
#define CLKID_VCLK0_DIV6 302
|
||||
#define CLKID_VCLK0_DIV12_EN 303
|
||||
#define CLKID_VCLK0_DIV12 304
|
||||
#define CLKID_VCLK1_SEL 305
|
||||
#define CLKID_VCLK1_IN 306
|
||||
#define CLKID_VCLK1_DIV 307
|
||||
#define CLKID_VCLK1 308
|
||||
#define CLKID_VCLK1_DIV1_EN 309
|
||||
#define CLKID_VCLK1_DIV2_EN 310
|
||||
#define CLKID_VCLK1_DIV2 311
|
||||
#define CLKID_VCLK1_DIV4_EN 312
|
||||
#define CLKID_VCLK1_DIV4 313
|
||||
#define CLKID_VCLK1_DIV6_EN 314
|
||||
#define CLKID_VCLK1_DIV6 315
|
||||
#define CLKID_VCLK1_DIV12_EN 316
|
||||
#define CLKID_VCLK1_DIV12 317
|
||||
#define CLKID_VDAC_SEL 318
|
||||
#define CLKID_VDAC 319
|
||||
#define CLKID_ENCODER0_SEL 320
|
||||
#define CLKID_ENCODER0 321
|
||||
#define CLKID_ENCODER1_SEL 322
|
||||
#define CLKID_ENCODER1 323
|
||||
#define CLKID_HDMITX0_PIXEL_SEL 324
|
||||
#define CLKID_HDMITX0_PIXEL 325
|
||||
#define CLKID_HDMITX0_FE_SEL 326
|
||||
#define CLKID_HDMITX0_FE 327
|
||||
#define CLKID_HDMITX1_PIXEL_SEL 328
|
||||
#define CLKID_HDMITX1_PIXEL 329
|
||||
#define CLKID_HDMITX1_FE_SEL 330
|
||||
#define CLKID_HDMITX1_FE 331
|
||||
#define CLKID_CSI_PHY_SEL 332
|
||||
#define CLKID_CSI_PHY_DIV 333
|
||||
#define CLKID_CSI_PHY 334
|
||||
#define CLKID_DSI0_MEAS_SEL 335
|
||||
#define CLKID_DSI0_MEAS_DIV 336
|
||||
#define CLKID_DSI0_MEAS 337
|
||||
#define CLKID_DSI1_MEAS_SEL 338
|
||||
#define CLKID_DSI1_MEAS_DIV 339
|
||||
#define CLKID_DSI1_MEAS 340
|
||||
|
||||
#endif /* __AMLOGIC_A9_PERIPHERALS_CLKC_H */
|
||||
Loading…
Reference in New Issue
Block a user