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arm64: dts: qcom: qcs8300-ride: enable pcie0 interface

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Add configurations in devicetree for PCIe0, board related gpios,
PMIC regulators, etc for qcs8300-ride board.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251128104928.4070050-4-ziyue.zhang@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Ziyue Zhang 2025-11-28 18:49:25 +08:00 committed by Bjorn Andersson
parent 46a7c01e7e
commit 33967eadb2
1 changed files with 42 additions and 0 deletions
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42
arch/arm64/boot/dts/qcom/qcs8300-ride.dts
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@ -353,6 +353,25 @@ &mdss_dp0_phy {
status = "okay";
};
&pcie0 {
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
status = "okay";
};
&pcieport0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
};
&pcie0_phy {
vdda-phy-supply = <&vreg_l6a>;
vdda-pll-supply = <&vreg_l5a>;
status = "okay";
};
&qupv3_id_0 {
status = "okay";
};
@ -398,6 +417,29 @@ &sdhc_1 {
};
&tlmm {
pcie0_default_state: pcie0-default-state {
wake-pins {
pins = "gpio0";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
clkreq-pins {
pins = "gpio1";
function = "pcie0_clkreq";
drive-strength = <2>;
bias-pull-up;
};
perst-pins {
pins = "gpio2";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
};
ethernet0_default: ethernet0-default-state {
ethernet0_mdc: ethernet0-mdc-pins {
pins = "gpio5";