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arm64: dts: rockchip: disable unrouted USB controllers and PHY on RK3399 Puma

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The u2phy1_host port is the part of the USB PHY1 (namely the
HOST1_DP/DM lanes) which routes directly to the USB2.0 HOST
controller[1]. The other lanes of the PHY are routed to the USB3.0 OTG
controller (dwc3), which we do use.

The HOST1_DP/DM lanes aren't routed on RK3399 Puma so let's simply
disable the USB2.0 controllers and associated part in USB2.0 PHY.

No intended functional change.

[1] https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.3%20Part2.pdf
    Chapter 2 USB2.0 PHY

Fixes: 2c66fc34e9 ("arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com>
Link: https://lore.kernel.org/r/20250425-onboard_usb_dev-v2-4-4a76a474a010@thaumatec.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Quentin Schulz 2025-04-25 17:18:09 +02:00 committed by Heiko Stuebner
parent d7cc532df9
commit 3373af1d76
1 changed files with 0 additions and 12 deletions
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12
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
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@ -585,10 +585,6 @@ &u2phy1 {
u2phy1_otg: otg-port {
status = "okay";
};
u2phy1_host: host-port {
status = "okay";
};
};
&usbdrd3_1 {
@ -622,11 +618,3 @@ hub_3_0: hub@2 {
vdd2-supply = <&vcc3v3_sys>;
};
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};