github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-06-05 04:56:13 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

Armv8 Juno/FVP updates for v6.2

Browse Source 
Just few addtions including updates to cache information on various
 platforms to align well with the bindings, addition of cache information
 on FVP Rev C model, addition of SPE to Foundation model and updates to
 LED node names.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAmOF8SgACgkQAEG6vDF+
 4ph7uhAAs+XsDmozvzn6q7XtgEDAsSmuXSSmdLawW9dOWBm4h9yP+b0ShfHasSlN
 Z/tg/Erc2IGLW6bYwam0JGLyzast2ifOVJfCe1M7Whfep3j2o/SV2eN43qnjSwwp
 enryQNw7hF9ShEHtvvBqruHg8BWNQqCBvJRAKHtemcXeXhaad0b32y53ahdbzB0o
 FAGD/i2KRJeghlw2s0lw4+jiV+W5UodoEZ4WbxQJSjTcUyqeDLiqfhs0KoHTJjaM
 s8rHKHRxRr+Wctibf25JW5iiBhe7ON9rb+KRVubI0jp9LVauO+dzujnR2dP+SbUC
 wc61U2G0QEZof+QCSYfVVQbuJ1bLVUzl6hJMl+c5VHSBq6x75jCCHdCq9PlTlXGl
 nmBPVP5haDgO17WsJuO5absawsBJehihwC0JLkk6bWnm15+XE7NnMDDLZRHSNuU9
 zterk4LVN7d94o+/WwK8XeZtzFfFS4l0OlIDBYWoP0hljvHc/p4jXOh2vvFucPmN
 L/YORmb8Vrj2Ql0NY+NPiHt1MDFIOftcYSufBuzzMQJw3pYQAQMFHKc3rUxB6Xee
 6CAikSuBWWO7qdY9yP8Fk+GceLrACSk5C/1pJOA2cBQiLw1whYI+4RRzn0g+Su9Z
 VN5KU6tP44tE0625ip5wLwcV1TiBa7ghKCezav+4b+TUFxLM0Yw=
 =Of6J
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmOHhtEACgkQmmx57+YA
 GNkW1g//dZ1xCZ7m0Zduhqp6dfLkC9IUyhkguIba3HsKLL5A1t4E5/AfZM7befQr
 rWZZTeeGQtpBlWo0/X2BjtNkcyDH02fU3Mk7mM3raOO/MF+C0IEAmaLWOkiekgYf
 dHg5ig2GKVI71wPRtYa0JfwFztgnkhGdMS+PSvELxDlisziVwSaGYOW+1DEZibU6
 hMTOZzePFvaI7Q6iP9N6uyLLiLnddrg2ar37z2ummsMgxVd51Eoe6IPzEa2B3bWB
 KswrPcVZ2XTINiOleMN9kE8awsZJOacIiNXP8oluffcu/03tLlwv3UYr5RDddtp8
 9K2GtXJ1wzvqXbpHo4a1AMwPkgUbcFgLZSl9ypZZP+afwIxxfunr7Ca0gdwBI4GR
 5cCrEih9SXGeegrzMz4wa5f5PuxDyeyRHzFzpnDX5z+6+8Q85tGUdDa6cazoBQyS
 U11Ty+zu+6NGWVPGz3e6udaJUkkQfF1TO0Kb9EtmNhOh6avj0J4kQT9Vx7PeoXpW
 LRPlBt8TLktS7/9jpAvdk0cLkULRqjLlONDRhdrIzGwW3+fMGVyMyWCWnNSu6ia/
 M57KTbfZsuq1p223arIC4z6YHPe0JKl5fgEaYRl9fVf3YcMPhrwllsLom5/xf25S
 2K7scuKw/AGE+2GSvVgyqyeqeeu+OaYpYkhtXZHVEMBuvBir7Oo=
 =GlOv
 -----END PGP SIGNATURE-----

Merge tag 'juno-updates-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt

Armv8 Juno/FVP updates for v6.2

Just few addtions including updates to cache information on various
platforms to align well with the bindings, addition of cache information
on FVP Rev C model, addition of SPE to Foundation model and updates to
LED node names.

* tag 'juno-updates-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  ARM: dts: vexpress: align LED node names with dtschema
  arm64: dts: fvp: Add information about L1 and L2 caches
  arm64: dts: fvp: Add SPE to Foundation FVP
  arm64: dts: Update cache properties for Arm Ltd platforms
  arm64: dts: juno: Add thermal critical trip points

Link: https://lore.kernel.org/r/20221129115111.2464233-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-11-30 17:26:26 +01:00
commit 33423a8bd2
10 changed files with 110 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
arch/arm/boot/dts/vexpress-v2m.dtsi
View File

@ -383,49 +383,49 @@ v2m_refclk32khz: refclk32khz {
leds {
compatible = "gpio-leds";
user1 {
led-user1 {
label = "v2m:green:user1";
gpios = <&v2m_led_gpios 0 0>;
linux,default-trigger = "heartbeat";
};
user2 {
led-user2 {
label = "v2m:green:user2";
gpios = <&v2m_led_gpios 1 0>;
linux,default-trigger = "mmc0";
};
user3 {
led-user3 {
label = "v2m:green:user3";
gpios = <&v2m_led_gpios 2 0>;
linux,default-trigger = "cpu0";
};
user4 {
led-user4 {
label = "v2m:green:user4";
gpios = <&v2m_led_gpios 3 0>;
linux,default-trigger = "cpu1";
};
user5 {
led-user5 {
label = "v2m:green:user5";
gpios = <&v2m_led_gpios 4 0>;
linux,default-trigger = "cpu2";
};
user6 {
led-user6 {
label = "v2m:green:user6";
gpios = <&v2m_led_gpios 5 0>;
linux,default-trigger = "cpu3";
};
user7 {
led-user7 {
label = "v2m:green:user7";
gpios = <&v2m_led_gpios 6 0>;
linux,default-trigger = "cpu4";
};
user8 {
led-user8 {
label = "v2m:green:user8";
gpios = <&v2m_led_gpios 7 0>;
linux,default-trigger = "cpu5";

1
arch/arm64/boot/dts/arm/corstone1000.dtsi
View File

@ -53,6 +53,7 @@ gic: interrupt-controller@1c000000 {
L2_0: l2-cache0 {
compatible = "cache";
cache-unified;
cache-level = <2>;
cache-size = <0x80000>;
cache-line-size = <64>;

6
arch/arm64/boot/dts/arm/foundation-v8.dtsi
View File

@ -58,6 +58,7 @@ cpu3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
};
@ -84,6 +85,11 @@ pmu {
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
};
spe-pmu {
compatible = "arm,statistical-profiling-extension-v1";
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
};
watchdog@2a440000 {
compatible = "arm,sbsa-gwdt";
reg = <0x0 0x2a440000 0 0x1000>,

73
arch/arm64/boot/dts/arm/fvp-base-revc.dts
View File

@ -47,48 +47,121 @@ cpu0: cpu@0 {
compatible = "arm,armv8";
reg = <0x0 0x000>;
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C0_L2>;
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C0_L2>;
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x200>;
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C0_L2>;
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x300>;
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C0_L2>;
};
cpu4: cpu@10000 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x10000>;
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C1_L2>;
};
cpu5: cpu@10100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x10100>;
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C1_L2>;
};
cpu6: cpu@10200 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x10200>;
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C1_L2>;
};
cpu7: cpu@10300 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x10300>;
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C1_L2>;
};
C0_L2: l2-cache0 {
compatible = "cache";
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
cache-level = <2>;
cache-unified;
};
C1_L2: l2-cache1 {
compatible = "cache";
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
cache-level = <2>;
cache-unified;
};
};

14
arch/arm64/boot/dts/arm/juno-base.dtsi
View File

@ -751,12 +751,26 @@ pmic {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 0>;
trips {
pmic_crit0: trip0 {
temperature = <90000>;
hysteresis = <2000>;
type = "critical";
};
};
};
soc {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&scpi_sensors0 3>;
trips {
soc_crit0: trip0 {
temperature = <80000>;
hysteresis = <2000>;
type = "critical";
};
};
};
big_cluster_thermal_zone: big-cluster {

2
arch/arm64/boot/dts/arm/juno-r1.dts
View File

@ -189,6 +189,7 @@ A53_3: cpu@103 {
A57_L2: l2-cache0 {
compatible = "cache";
cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@ -197,6 +198,7 @@ A57_L2: l2-cache0 {
A53_L2: l2-cache1 {
compatible = "cache";
cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;

2
arch/arm64/boot/dts/arm/juno-r2.dts
View File

@ -195,6 +195,7 @@ A53_3: cpu@103 {
A72_L2: l2-cache0 {
compatible = "cache";
cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@ -203,6 +204,7 @@ A72_L2: l2-cache0 {
A53_L2: l2-cache1 {
compatible = "cache";
cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;

2
arch/arm64/boot/dts/arm/juno.dts
View File

@ -194,6 +194,7 @@ A53_3: cpu@103 {
A57_L2: l2-cache0 {
compatible = "cache";
cache-unified;
cache-size = <0x200000>;
cache-line-size = <64>;
cache-sets = <2048>;
@ -202,6 +203,7 @@ A57_L2: l2-cache0 {
A53_L2: l2-cache1 {
compatible = "cache";
cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>;

1
arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
View File

@ -71,6 +71,7 @@ cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
};

1
arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
View File

@ -57,6 +57,7 @@ cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
};