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drm: renesas: rz-du: Move mode_valid logic to per-SoC clock limits

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Move pixel clock validation from a fixed encoder check to per SoC
constraints stored in rzg2l_du_device_info.

Pixel clock limits differ across SoCs in the RZ DU family and cannot be
expressed by a single shared rule. For example, RZ/G2UL and RZ/G2L limit
the DPAD0 pixel clock to a narrow window, while other SoCs such as
RZ/T2H require a wider operating range.

Add mode_clock_min and mode_clock_max fields to rzg2l_du_device_info to
describe the supported pixel clock range for each SoC. Update
rzg2l_du_encoder_mode_valid() to check these bounds when evaluating
DPAD0 outputs, returning MODE_CLOCK_LOW when the pixel clock falls
below mode_clock_min and MODE_CLOCK_HIGH when it exceeds mode_clock_max.

Populate the pixel clock limits for both the RZ/G2UL (R9A07G043U) and
RZ/G2L (R9A07G044) variants to a minimum of 20875 kHz and a maximum of
83500 kHz.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/20260519160825.4082566-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
This commit is contained in:
Lad Prabhakar 2026-05-19 17:08:24 +01:00 committed by Biju Das
parent 62ca607fcb
commit 332d72b951
3 changed files with 17 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
View File

@ -35,6 +35,8 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g043u_info = {
.port = 0,
},
},
.mode_clock_min = 20875,
.mode_clock_max = 83500,
};
static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = {
@ -48,7 +50,9 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = {
.possible_outputs = BIT(0),
.port = 1,
}
}
},
.mode_clock_min = 20875,
.mode_clock_max = 83500,
};
static const struct rzg2l_du_device_info rzg2l_du_r9a09g057_info = {

4
drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
View File

@ -44,10 +44,14 @@ struct rzg2l_du_output_routing {
* struct rzg2l_du_device_info - DU model-specific information
* @channels_mask: bit mask of available DU channels
* @routes: array of CRTC to output routes, indexed by output (RZG2L_DU_OUTPUT_*)
* @mode_clock_min: minimum pixel clock in kHz
* @mode_clock_max: maximum pixel clock in kHz
*/
struct rzg2l_du_device_info {
unsigned int channels_mask;
struct rzg2l_du_output_routing routes[RZG2L_DU_OUTPUT_MAX];
u32 mode_clock_min;
u32 mode_clock_max;
};
#define RZG2L_DU_MAX_CRTCS 1

9
drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
View File

@ -50,8 +50,15 @@ rzg2l_du_encoder_mode_valid(struct drm_encoder *encoder,
const struct drm_display_mode *mode)
{
struct rzg2l_du_encoder *renc = to_rzg2l_encoder(encoder);
struct rzg2l_du_device *rcdu = to_rzg2l_du_device(renc->base.dev);
const struct rzg2l_du_device_info *info = rcdu->info;
if (renc->output == RZG2L_DU_OUTPUT_DPAD0 && mode->clock > 83500)
if (renc->output != RZG2L_DU_OUTPUT_DPAD0)
return MODE_OK;
if (mode->clock < info->mode_clock_min)
return MODE_CLOCK_LOW;
if (mode->clock > info->mode_clock_max)
return MODE_CLOCK_HIGH;
return MODE_OK;