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riscv: dts: add initial support for EIC7700 SoC
Add initial support for EIC7700 SoC that uses a SiFive Quad-Core P550 CPU cluster. This file is expected to grow as more device drivers are added to the kernel. Signed-off-by: Min Lin <linmin@eswincomputing.com> Co-developed-by: Pritesh Patel <pritesh.patel@einfochips.com> Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com> Co-developed-by: Darshan Prajapati <darshan.prajapati@einfochips.com> Signed-off-by: Darshan Prajapati <darshan.prajapati@einfochips.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com> Link: https://lore.kernel.org/r/20250825132427.1618089-6-pinkesh.vaghela@einfochips.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Min Lin
Arnd Bergmann
parent
21b5a7ace6
commit
3329e2f3b5
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@ -9079,7 +9079,9 @@ M: Min Lin <linmin@eswincomputing.com>
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M: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
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M: Pritesh Patel <pritesh.patel@einfochips.com>
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S: Maintained
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T: git https://github.com/eswincomputing/linux-next.git
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F: Documentation/devicetree/bindings/riscv/eswin.yaml
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F: arch/riscv/boot/dts/eswin/
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ET131X NETWORK DRIVER
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M: Mark Einon <mark.einon@gmail.com>
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345
arch/riscv/boot/dts/eswin/eic7700.dtsi
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345
arch/riscv/boot/dts/eswin/eic7700.dtsi
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@ -0,0 +1,345 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (c) 2024 Beijing ESWIN Computing Technology Co., Ltd.
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*/
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <1000000>;
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cpu0: cpu@0 {
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compatible = "sifive,p550", "riscv";
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device_type = "cpu";
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d-cache-block-size = <64>;
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d-cache-sets = <128>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv48";
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next-level-cache = <&l2_cache_0>;
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reg = <0x0>;
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf",
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"zba", "zbb", "zicsr", "zifencei";
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tlb-split;
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu1: cpu@1 {
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compatible = "sifive,p550", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <128>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv48";
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next-level-cache = <&l2_cache_1>;
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reg = <0x1>;
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf",
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"zba", "zbb", "zicsr", "zifencei";
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tlb-split;
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cpu1_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu2: cpu@2 {
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compatible = "sifive,p550", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <128>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv48";
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next-level-cache = <&l2_cache_2>;
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reg = <0x2>;
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf",
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"zba", "zbb", "zicsr", "zifencei";
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tlb-split;
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cpu2_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu3: cpu@3 {
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compatible = "sifive,p550", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <128>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv48";
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next-level-cache = <&l2_cache_3>;
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reg = <0x3>;
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf",
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"zba", "zbb", "zicsr", "zifencei";
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tlb-split;
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cpu3_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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l2_cache_0: l2-cache0 {
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compatible = "cache";
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cache-block-size = <64>;
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cache-level = <2>;
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cache-sets = <512>;
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cache-size = <262144>;
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cache-unified;
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next-level-cache = <&ccache>;
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};
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l2_cache_1: l2-cache1 {
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compatible = "cache";
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cache-block-size = <64>;
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cache-level = <2>;
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cache-sets = <512>;
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cache-size = <262144>;
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cache-unified;
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next-level-cache = <&ccache>;
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};
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l2_cache_2: l2-cache2 {
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compatible = "cache";
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cache-block-size = <64>;
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cache-level = <2>;
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cache-sets = <512>;
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cache-size = <262144>;
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cache-unified;
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next-level-cache = <&ccache>;
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};
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l2_cache_3: l2-cache3 {
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compatible = "cache";
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cache-block-size = <64>;
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cache-level = <2>;
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cache-sets = <512>;
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cache-size = <262144>;
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cache-unified;
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next-level-cache = <&ccache>;
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};
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};
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pmu {
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compatible = "riscv,pmu";
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riscv,event-to-mhpmcounters =
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<0x00001 0x00001 0x00000001>,
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<0x00002 0x00002 0x00000004>,
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<0x00004 0x00006 0x00000078>,
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<0x10009 0x10009 0x00000078>,
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<0x10019 0x10019 0x00000078>,
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<0x10021 0x10021 0x00000078>;
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riscv,event-to-mhpmevent =
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<0x00004 0x00000000 0x00000202>,
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<0x00005 0x00000000 0x00004000>,
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<0x00006 0x00000000 0x00002001>,
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<0x10009 0x00000000 0x00000102>,
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<0x10019 0x00000000 0x00001002>,
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<0x10021 0x00000000 0x00000802>;
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riscv,raw-event-to-mhpmcounters =
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<0x00000000 0x00000000 0xffffffff 0xfc0000ff 0x00000078>,
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<0x00000000 0x00000001 0xffffffff 0xfffe07ff 0x00000078>,
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<0x00000000 0x00000002 0xffffffff 0xfffe00ff 0x00000078>,
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<0x00000000 0x00000003 0xfffffffc 0x000000ff 0x00000078>,
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<0x00000000 0x00000004 0xffffffc0 0x000000ff 0x00000078>,
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<0x00000000 0x00000005 0xffffffff 0xfffffdff 0x00000078>,
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<0x00000000 0x00000006 0xfffffe00 0x110204ff 0x00000078>,
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<0x00000000 0x00000007 0xffffffff 0xf00000ff 0x00000078>,
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<0x00000000 0x00000008 0xfffffe04 0x000000ff 0x00000078>,
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<0x00000000 0x00000009 0xffffffff 0xffffc0ff 0x00000078>,
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<0x00000000 0x0000000a 0xffffffff 0xf00000ff 0x00000078>,
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<0x00000000 0x0000000b 0xffffffff 0xfffffcff 0x00000078>,
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<0x00000000 0x0000000c 0xfffffff0 0x000000ff 0x00000078>,
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<0x00000000 0x0000000d 0xffffffff 0x800000ff 0x00000078>,
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<0x00000000 0x0000000e 0xffffffff 0xf80000ff 0x00000078>,
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<0x00000000 0x0000000f 0xfffffffc 0x000000ff 0x00000078>;
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};
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soc {
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compatible = "simple-bus";
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ranges;
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interrupt-parent = <&plic>;
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#address-cells = <2>;
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#size-cells = <2>;
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dma-noncoherent;
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clint: timer@2000000 {
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compatible = "eswin,eic7700-clint", "sifive,clint0";
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reg = <0x0 0x02000000 0x0 0x10000>;
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interrupts-extended =
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<&cpu0_intc 3>, <&cpu0_intc 7>,
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<&cpu1_intc 3>, <&cpu1_intc 7>,
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<&cpu2_intc 3>, <&cpu2_intc 7>,
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<&cpu3_intc 3>, <&cpu3_intc 7>;
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};
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ccache: cache-controller@2010000 {
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compatible = "eswin,eic7700-l3-cache", "sifive,ccache0", "cache";
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reg = <0x0 0x2010000 0x0 0x4000>;
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interrupts = <1>, <3>, <4>, <2>;
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cache-block-size = <64>;
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cache-level = <3>;
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cache-sets = <4096>;
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cache-size = <4194304>;
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cache-unified;
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};
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plic: interrupt-controller@c000000 {
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compatible = "eswin,eic7700-plic", "sifive,plic-1.0.0";
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reg = <0x0 0xc000000 0x0 0x4000000>;
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interrupt-controller;
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interrupts-extended =
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<&cpu0_intc 11>, <&cpu0_intc 9>,
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<&cpu1_intc 11>, <&cpu1_intc 9>,
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<&cpu2_intc 11>, <&cpu2_intc 9>,
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<&cpu3_intc 11>, <&cpu3_intc 9>;
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riscv,ndev = <520>;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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uart0: serial@50900000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x50900000 0x0 0x10000>;
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interrupts = <100>;
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clock-frequency = <200000000>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart1: serial@50910000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x50910000 0x0 0x10000>;
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interrupts = <101>;
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clock-frequency = <200000000>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart2: serial@50920000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x50920000 0x0 0x10000>;
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interrupts = <102>;
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clock-frequency = <200000000>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart3: serial@50930000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x50930000 0x0 0x10000>;
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interrupts = <103>;
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clock-frequency = <200000000>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart4: serial@50940000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x50940000 0x0 0x10000>;
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interrupts = <104>;
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clock-frequency = <200000000>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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gpio@51600000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0 0x51600000 0x0 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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gpioA: gpio-port@0 {
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compatible = "snps,dw-apb-gpio-port";
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts =
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<303>, <304>, <305>, <306>, <307>, <308>, <309>,
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<310>, <311>, <312>, <313>, <314>, <315>, <316>,
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<317>, <318>, <319>, <320>, <321>, <322>, <323>,
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<324>, <325>, <326>, <327>, <328>, <329>, <330>,
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<331>, <332>, <333>, <334>;
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gpio-controller;
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ngpios = <32>;
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#gpio-cells = <2>;
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};
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gpioB: gpio-port@1 {
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compatible = "snps,dw-apb-gpio-port";
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reg = <1>;
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gpio-controller;
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ngpios = <32>;
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#gpio-cells = <2>;
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};
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gpioC: gpio-port@2 {
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compatible = "snps,dw-apb-gpio-port";
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reg = <2>;
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gpio-controller;
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ngpios = <32>;
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#gpio-cells = <2>;
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};
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gpioD: gpio-port@3 {
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compatible = "snps,dw-apb-gpio-port";
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reg = <3>;
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gpio-controller;
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ngpios = <16>;
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#gpio-cells = <2>;
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};
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};
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};
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};
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