From 332021557104ccf46d40ef7bae3f12a53f56edf3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 7 Apr 2026 21:30:15 +0300 Subject: [PATCH] drm/i915/dp: Don't use DP link min bpp for the FRL link bandwidth check MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit intel_dp_mode_min_link_bpp_x16() gives us the min bpp for the DP link before the PCON, however intel_dp_mode_valid_downstream() is trying to check for sufficient bandwidth on the HDMI FRL link after the PCON. So the use of intel_dp_mode_min_link_bpp_x16() here is incorrect. Presumably even with FRL HDMI still can't go below 8bpc, so we should just use that to give us the minimum required FRL bandwidth. And this needs to account for the sink format (for 4:2:0 sub-sampling) since that is what will be flowing over the HDMI link. Cc: Ankit Nautiyal Cc: Nicolas Frattaroli Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260407183015.16256-1-ville.syrjala@linux.intel.com Reviewed-by: Ankit Nautiyal Reviewed-by: Nicolas Frattaroli --- drivers/gpu/drm/i915/display/intel_dp.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index ff3904b77492..b8b6d62fb275 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1317,6 +1317,15 @@ intel_dp_tmds_clock_valid(struct intel_dp *intel_dp, return MODE_OK; } +static int frl_required_bw(int clock, int bpc, + enum intel_output_format sink_format) +{ + if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) + clock /= 2; + + return clock * bpc * 3; +} + static enum drm_mode_status intel_dp_mode_valid_downstream(struct intel_connector *connector, const struct drm_display_mode *mode, @@ -1327,13 +1336,14 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, enum drm_mode_status status; enum intel_output_format sink_format; + sink_format = intel_dp_sink_format(connector, mode); + /* If PCON supports FRL MODE, check FRL bandwidth constraints */ if (intel_dp->dfp.pcon_max_frl_bw) { - int link_bpp_x16 = intel_dp_mode_min_link_bpp_x16(connector, mode); - int target_bw; - int max_frl_bw; + int target_bw, max_frl_bw; - target_bw = fxp_q4_to_int_roundup(link_bpp_x16) * target_clock; + /* Assume 8bpc for the FRL bandwidth check */ + target_bw = frl_required_bw(target_clock, 8, sink_format); max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; @@ -1350,8 +1360,6 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, target_clock > intel_dp->dfp.max_dotclock) return MODE_CLOCK_HIGH; - sink_format = intel_dp_sink_format(connector, mode); - /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ status = intel_dp_tmds_clock_valid(intel_dp, target_clock, 8, sink_format, true);