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arm64: dts: imx93: add cache info

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i.MX93 features two Cortex-A55 cores with per core L1 Instruction
cache size 32KB, L1 data cache size 32KB, per core L2 cache 64KB, and
unified 256KB L3 cache.

Add the cache info to remove cacheinfo warnings at boot:
"cacheinfo: Unable to detect cache hierarchy for CPU 0"

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefan Wahren <wahrenst@gmx.net>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Peng Fan 2024-08-01 16:11:11 +08:00 committed by Shawn Guo
parent 280899d46f
commit 331c038a95
1 changed files with 42 additions and 0 deletions
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42
arch/arm64/boot/dts/freescale/imx93.dtsi
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@ -69,6 +69,13 @@ A55_0: cpu@0 {
enable-method = "psci";
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
i-cache-sets = <128>;
d-cache-size = <32768>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_cache_l0>;
};
A55_1: cpu@100 {
@ -78,8 +85,43 @@ A55_1: cpu@100 {
enable-method = "psci";
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
i-cache-sets = <128>;
d-cache-size = <32768>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_cache_l1>;
};
l2_cache_l0: l2-cache-l0 {
compatible = "cache";
cache-size = <65536>;
cache-line-size = <64>;
cache-sets = <256>;
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
l2_cache_l1: l2-cache-l1 {
compatible = "cache";
cache-size = <65536>;
cache-line-size = <64>;
cache-sets = <256>;
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
l3_cache: l3-cache {
compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <256>;
cache-level = <3>;
cache-unified;
};
};
osc_32k: clock-osc-32k {