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drm/amd/display: Correct hubp GfxVersion verification

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[Why]
DcGfxBase case was not accounted for in hubp program tiling functions,
causing tiling corruption on PNP.

[How]
Add handling for DcGfxBase so that tiling gets properly cleared.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Nicholas Carbones <ncarbone@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nicholas Carbones 2026-01-28 15:52:46 -05:00 committed by Alex Deucher
parent 6386a0bcdb
commit 3303aa64e7
3 changed files with 46 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
View File

@ -145,21 +145,26 @@ void hubp1_program_tiling(
{ {
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
ASSERT(info->gfxversion == DcGfxVersion9); ASSERT(info->gfxversion == DcGfxVersion9 || info->gfxversion == DcGfxBase);
REG_UPDATE_6(DCSURF_ADDR_CONFIG, if (info->gfxversion == DcGfxVersion9) {
NUM_PIPES, log_2(info->gfx9.num_pipes), REG_UPDATE_6(DCSURF_ADDR_CONFIG,
NUM_BANKS, log_2(info->gfx9.num_banks), NUM_PIPES, log_2(info->gfx9.num_pipes),
PIPE_INTERLEAVE, info->gfx9.pipe_interleave, NUM_BANKS, log_2(info->gfx9.num_banks),
NUM_SE, log_2(info->gfx9.num_shader_engines), PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se), NUM_SE, log_2(info->gfx9.num_shader_engines),
MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se),
MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
REG_UPDATE_4(DCSURF_TILING_CONFIG,
SW_MODE, info->gfx9.swizzle,
META_LINEAR, info->gfx9.meta_linear,
RB_ALIGNED, info->gfx9.rb_aligned,
PIPE_ALIGNED, info->gfx9.pipe_aligned);
} else {
hubp1_clear_tiling(&hubp1->base);
}
REG_UPDATE_4(DCSURF_TILING_CONFIG,
SW_MODE, info->gfx9.swizzle,
META_LINEAR, info->gfx9.meta_linear,
RB_ALIGNED, info->gfx9.rb_aligned,
PIPE_ALIGNED, info->gfx9.pipe_aligned);
} }
void hubp1_program_size( void hubp1_program_size(

24
drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
View File

@ -313,18 +313,22 @@ static void hubp2_program_tiling(
const struct dc_tiling_info *info, const struct dc_tiling_info *info,
const enum surface_pixel_format pixel_format) const enum surface_pixel_format pixel_format)
{ {
ASSERT(info->gfxversion == DcGfxVersion9); ASSERT(info->gfxversion == DcGfxVersion9 || info->gfxversion == DcGfxBase);
REG_UPDATE_3(DCSURF_ADDR_CONFIG, if (info->gfxversion == DcGfxVersion9) {
NUM_PIPES, log_2(info->gfx9.num_pipes), REG_UPDATE_3(DCSURF_ADDR_CONFIG,
PIPE_INTERLEAVE, info->gfx9.pipe_interleave, NUM_PIPES, log_2(info->gfx9.num_pipes),
MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
REG_UPDATE_4(DCSURF_TILING_CONFIG, REG_UPDATE_4(DCSURF_TILING_CONFIG,
SW_MODE, info->gfx9.swizzle, SW_MODE, info->gfx9.swizzle,
META_LINEAR, 0, META_LINEAR, 0,
RB_ALIGNED, 0, RB_ALIGNED, 0,
PIPE_ALIGNED, 0); PIPE_ALIGNED, 0);
} else {
hubp2_clear_tiling(&hubp2->base);
}
} }
void hubp2_program_size( void hubp2_program_size(

24
drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
View File

@ -321,18 +321,22 @@ void hubp3_program_tiling(
const struct dc_tiling_info *info, const struct dc_tiling_info *info,
const enum surface_pixel_format pixel_format) const enum surface_pixel_format pixel_format)
{ {
ASSERT(info->gfxversion == DcGfxVersion9); ASSERT(info->gfxversion == DcGfxVersion9 || info->gfxversion == DcGfxBase);
REG_UPDATE_4(DCSURF_ADDR_CONFIG, if (info->gfxversion == DcGfxVersion9) {
NUM_PIPES, log_2(info->gfx9.num_pipes), REG_UPDATE_4(DCSURF_ADDR_CONFIG,
PIPE_INTERLEAVE, info->gfx9.pipe_interleave, NUM_PIPES, log_2(info->gfx9.num_pipes),
MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags), PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
NUM_PKRS, log_2(info->gfx9.num_pkrs)); MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags),
NUM_PKRS, log_2(info->gfx9.num_pkrs));
REG_UPDATE_3(DCSURF_TILING_CONFIG, REG_UPDATE_3(DCSURF_TILING_CONFIG,
SW_MODE, info->gfx9.swizzle, SW_MODE, info->gfx9.swizzle,
META_LINEAR, info->gfx9.meta_linear, META_LINEAR, info->gfx9.meta_linear,
PIPE_ALIGNED, info->gfx9.pipe_aligned); PIPE_ALIGNED, info->gfx9.pipe_aligned);
} else {
hubp3_clear_tiling(&hubp2->base);
}
} }