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drm/amd/display: Update SW state correctly for FCLK

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FCLK not supported for DCN321, but still need to update the software
state accordingly to prevent unneeded full updates in driver

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alvin Lee 2022-05-25 13:34:07 -04:00 committed by Alex Deucher
parent a3a885878e
commit 32e8ab05ed
1 changed files with 3 additions and 3 deletions
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6
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
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@ -431,12 +431,12 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
}
if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 &&
should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) {
if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support) &&
clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21) {
clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
/* To disable FCLK P-state switching, send FCLK_PSTATE_NOTSUPPORTED message to PMFW */
if (!clk_mgr_base->clks.fclk_p_state_change_support) {
if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && !clk_mgr_base->clks.fclk_p_state_change_support) {
/* Handle code for sending a message to PMFW that FCLK P-state change is not supported */
dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_NOTSUPPORTED);
}