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arm64: dts: mediatek: mt7988: add switch node

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Add mt7988 builtin mt753x switch nodes.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250709111147.11843-11-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Frank Wunderlich 2025-07-09 13:09:46 +02:00 committed by Matthias Brugger
parent 65f0e39701
commit 32d5a82c5d
1 changed files with 148 additions and 0 deletions
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148
arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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@ -742,6 +742,154 @@ ethsys: clock-controller@15000000 {
#reset-cells = <1>;
};
switch: switch@15020000 {
compatible = "mediatek,mt7988-switch";
reg = <0 0x15020000 0 0x8000>;
interrupt-controller;
#interrupt-cells = <1>;
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
resets = <&ethwarp MT7988_ETHWARP_RST_SWITCH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
gsw_port0: port@0 {
reg = <0>;
phy-handle = <&gsw_phy0>;
phy-mode = "internal";
};
gsw_port1: port@1 {
reg = <1>;
phy-handle = <&gsw_phy1>;
phy-mode = "internal";
};
gsw_port2: port@2 {
reg = <2>;
phy-handle = <&gsw_phy2>;
phy-mode = "internal";
};
gsw_port3: port@3 {
reg = <3>;
phy-handle = <&gsw_phy3>;
phy-mode = "internal";
};
port@6 {
reg = <6>;
ethernet = <&gmac0>;
phy-mode = "internal";
fixed-link {
speed = <10000>;
full-duplex;
pause;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
mediatek,pio = <&pio>;
gsw_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
interrupts = <0>;
nvmem-cells = <&phy_calibration_p0>;
nvmem-cell-names = "phy-cal-data";
leds {
#address-cells = <1>;
#size-cells = <0>;
gsw_phy0_led0: led@0 {
reg = <0>;
status = "disabled";
};
gsw_phy0_led1: led@1 {
reg = <1>;
status = "disabled";
};
};
};
gsw_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupts = <1>;
nvmem-cells = <&phy_calibration_p1>;
nvmem-cell-names = "phy-cal-data";
leds {
#address-cells = <1>;
#size-cells = <0>;
gsw_phy1_led0: led@0 {
reg = <0>;
status = "disabled";
};
gsw_phy1_led1: led@1 {
reg = <1>;
status = "disabled";
};
};
};
gsw_phy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
interrupts = <2>;
nvmem-cells = <&phy_calibration_p2>;
nvmem-cell-names = "phy-cal-data";
leds {
#address-cells = <1>;
#size-cells = <0>;
gsw_phy2_led0: led@0 {
reg = <0>;
status = "disabled";
};
gsw_phy2_led1: led@1 {
reg = <1>;
status = "disabled";
};
};
};
gsw_phy3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
interrupts = <3>;
nvmem-cells = <&phy_calibration_p3>;
nvmem-cell-names = "phy-cal-data";
leds {
#address-cells = <1>;
#size-cells = <0>;
gsw_phy3_led0: led@0 {
reg = <0>;
status = "disabled";
};
gsw_phy3_led1: led@1 {
reg = <1>;
status = "disabled";
};
};
};
};
};
ethwarp: clock-controller@15031000 {
compatible = "mediatek,mt7988-ethwarp";
reg = <0 0x15031000 0 0x1000>;