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include: drm: rockchip_drm.h: remove those old unsued file
Thoes file were introduced by Commit bdafdac384
(rk3288 chromium: drm grafic fb support for x11 mali gpu), for now we have the
mainline rockchip drm code, no need those old head files, let's removed them.
Change-Id: I325a5b7981ac5478349f276f8811b1b51e40c564
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
This commit is contained in:
Yakir Yang
Gerrit Code Review
parent
01128dd5ad
commit
32a1a6180d
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@ -1,100 +0,0 @@
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/* rockchip_drm.h
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* Authors:
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* Inki Dae <inki.dae@samsung.com>
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* Joonyoung Shim <jy0922.shim@samsung.com>
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* Seung-Woo Kim <sw0312.kim@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _rockchip_DRM_H_
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#define _rockchip_DRM_H_
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#include <uapi/drm/rockchip_drm.h>
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/**
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* A structure for lcd panel information.
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*
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* @timing: default video mode for initializing
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* @width_mm: physical size of lcd width.
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* @height_mm: physical size of lcd height.
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*/
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struct rockchip_drm_panel_info {
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struct fb_videomode timing;
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u32 width_mm;
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u32 height_mm;
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};
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/**
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* Platform Specific Structure for DRM based FIMD.
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*
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* @panel: default panel info for initializing
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* @default_win: default window layer number to be used for UI.
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* @bpp: default bit per pixel.
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*/
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struct rockchip_drm_fimd_pdata {
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struct rockchip_drm_panel_info panel;
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u32 vidcon0;
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u32 vidcon1;
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unsigned int default_win;
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unsigned int bpp;
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};
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/**
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* Platform Specific Structure for DRM based HDMI.
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*
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* @hdmi_dev: device point to specific hdmi driver.
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* @mixer_dev: device point to specific mixer driver.
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*
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* this structure is used for common hdmi driver and each device object
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* would be used to access specific device driver(hdmi or mixer driver)
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*/
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struct rockchip_drm_common_hdmi_pd {
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struct device *hdmi_dev;
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struct device *mixer_dev;
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};
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/**
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* Platform Specific Structure for DRM based HDMI core.
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*
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* @is_v13: set if hdmi version 13 is.
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* @cfg_hpd: function pointer to configure hdmi hotplug detection pin
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* @get_hpd: function pointer to get value of hdmi hotplug detection pin
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*/
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struct rockchip_drm_hdmi_pdata {
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bool is_v13;
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void (*cfg_hpd)(bool external);
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int (*get_hpd)(void);
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};
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/**
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* Platform Specific Structure for DRM based IPP.
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*
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* @inv_pclk: if set 1. invert pixel clock
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* @inv_vsync: if set 1. invert vsync signal for wb
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* @inv_href: if set 1. invert href signal
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* @inv_hsync: if set 1. invert hsync signal for wb
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*/
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struct rockchip_drm_ipp_pol {
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unsigned int inv_pclk;
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unsigned int inv_vsync;
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unsigned int inv_href;
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unsigned int inv_hsync;
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};
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/**
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* Platform Specific Structure for DRM based FIMC.
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*
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* @pol: current hardware block polarity settings.
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* @clk_rate: current hardware clock rate.
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*/
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struct rockchip_drm_fimc_pdata {
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struct rockchip_drm_ipp_pol pol;
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int clk_rate;
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};
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#endif /* _rockchip_DRM_H_ */
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@ -1,390 +0,0 @@
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/*
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*
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* Copyright (C) ROCKCHIP, Inc.
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*Author:yzq<yzq@rock-chips.com>
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _UAPI_ROCKCHIP_DRM_H_
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#define _UAPI_ROCKCHIP_DRM_H_
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#include <drm/drm.h>
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/**
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* User-desired buffer creation information structure.
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*
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* @size: user-desired memory allocation size.
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* - this size value would be page-aligned internally.
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* @flags: user request for setting memory type or cache attributes.
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* @handle: returned a handle to created gem object.
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* - this handle will be set by gem module of kernel side.
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*/
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struct drm_rockchip_gem_create {
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uint64_t size;
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unsigned int flags;
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unsigned int handle;
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};
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/**
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* A structure for getting buffer offset.
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*
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* @handle: a pointer to gem object created.
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* @pad: just padding to be 64-bit aligned.
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* @offset: relatived offset value of the memory region allocated.
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* - this value should be set by user.
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*/
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struct drm_rockchip_gem_map_off {
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unsigned int handle;
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unsigned int pad;
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uint64_t offset;
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};
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/**
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* A structure for mapping buffer.
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*
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* @handle: a handle to gem object created.
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* @pad: just padding to be 64-bit aligned.
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* @size: memory size to be mapped.
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* @mapped: having user virtual address mmaped.
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* - this variable would be filled by exynos gem module
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* of kernel side with user virtual address which is allocated
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* by do_mmap().
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*/
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struct drm_rockchip_gem_mmap {
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unsigned int handle;
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unsigned int pad;
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uint64_t size;
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uint64_t mapped;
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};
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/**
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* A structure to gem information.
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*
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* @handle: a handle to gem object created.
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* @flags: flag value including memory type and cache attribute and
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* this value would be set by driver.
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* @size: size to memory region allocated by gem and this size would
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* be set by driver.
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*/
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struct drm_rockchip_gem_info {
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unsigned int handle;
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unsigned int flags;
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uint64_t size;
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};
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/**
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* A structure for user connection request of virtual display.
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*
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* @connection: indicate whether doing connetion or not by user.
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* @extensions: if this value is 1 then the vidi driver would need additional
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* 128bytes edid data.
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* @edid: the edid data pointer from user side.
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*/
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struct drm_rockchip_vidi_connection {
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unsigned int connection;
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unsigned int extensions;
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uint64_t edid;
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};
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/* memory type definitions. */
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enum e_drm_rockchip_gem_mem_type {
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/* Physically Continuous memory and used as default. */
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ROCKCHIP_BO_CONTIG = 0 << 0,
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/* Physically Non-Continuous memory. */
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ROCKCHIP_BO_NONCONTIG = 1 << 0,
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/* non-cachable mapping and used as default. */
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ROCKCHIP_BO_NONCACHABLE = 0 << 1,
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/* cachable mapping. */
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ROCKCHIP_BO_CACHABLE = 1 << 1,
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/* write-combine mapping. */
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ROCKCHIP_BO_WC = 1 << 2,
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ROCKCHIP_BO_MASK = ROCKCHIP_BO_NONCONTIG | ROCKCHIP_BO_CACHABLE |
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ROCKCHIP_BO_WC
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};
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struct drm_rockchip_g2d_get_ver {
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__u32 major;
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__u32 minor;
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};
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struct drm_rockchip_g2d_cmd {
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__u32 offset;
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__u32 data;
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};
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enum drm_rockchip_g2d_buf_type {
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G2D_BUF_USERPTR = 1 << 31,
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};
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enum drm_rockchip_g2d_event_type {
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G2D_EVENT_NOT,
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G2D_EVENT_NONSTOP,
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G2D_EVENT_STOP, /* not yet */
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};
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struct drm_rockchip_g2d_userptr {
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unsigned long userptr;
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unsigned long size;
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};
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struct drm_rockchip_g2d_set_cmdlist {
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__u64 cmd;
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__u64 cmd_buf;
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__u32 cmd_nr;
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__u32 cmd_buf_nr;
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/* for g2d event */
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__u64 event_type;
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__u64 user_data;
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};
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struct drm_rockchip_g2d_exec {
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__u64 async;
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};
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enum drm_rockchip_ops_id {
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ROCKCHIP_DRM_OPS_SRC,
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ROCKCHIP_DRM_OPS_DST,
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ROCKCHIP_DRM_OPS_MAX,
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};
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struct drm_rockchip_sz {
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__u32 hsize;
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__u32 vsize;
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};
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struct drm_rockchip_pos {
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__u32 x;
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__u32 y;
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__u32 w;
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__u32 h;
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};
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enum drm_rockchip_flip {
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ROCKCHIP_DRM_FLIP_NONE = (0 << 0),
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ROCKCHIP_DRM_FLIP_VERTICAL = (1 << 0),
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ROCKCHIP_DRM_FLIP_HORIZONTAL = (1 << 1),
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ROCKCHIP_DRM_FLIP_BOTH = ROCKCHIP_DRM_FLIP_VERTICAL |
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ROCKCHIP_DRM_FLIP_HORIZONTAL,
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};
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enum drm_rockchip_degree {
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ROCKCHIP_DRM_DEGREE_0,
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ROCKCHIP_DRM_DEGREE_90,
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ROCKCHIP_DRM_DEGREE_180,
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ROCKCHIP_DRM_DEGREE_270,
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};
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enum drm_rockchip_planer {
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ROCKCHIP_DRM_PLANAR_Y,
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ROCKCHIP_DRM_PLANAR_CB,
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ROCKCHIP_DRM_PLANAR_CR,
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ROCKCHIP_DRM_PLANAR_MAX,
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};
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/**
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* A structure for ipp supported property list.
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*
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* @version: version of this structure.
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* @ipp_id: id of ipp driver.
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* @count: count of ipp driver.
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* @writeback: flag of writeback supporting.
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* @flip: flag of flip supporting.
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* @degree: flag of degree information.
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* @csc: flag of csc supporting.
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* @crop: flag of crop supporting.
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* @scale: flag of scale supporting.
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* @refresh_min: min hz of refresh.
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* @refresh_max: max hz of refresh.
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* @crop_min: crop min resolution.
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* @crop_max: crop max resolution.
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* @scale_min: scale min resolution.
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* @scale_max: scale max resolution.
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*/
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struct drm_rockchip_ipp_prop_list {
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__u32 version;
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__u32 ipp_id;
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__u32 count;
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__u32 writeback;
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__u32 flip;
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__u32 degree;
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__u32 csc;
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__u32 crop;
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__u32 scale;
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__u32 refresh_min;
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__u32 refresh_max;
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__u32 reserved;
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struct drm_rockchip_sz crop_min;
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struct drm_rockchip_sz crop_max;
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struct drm_rockchip_sz scale_min;
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struct drm_rockchip_sz scale_max;
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};
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/**
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* A structure for ipp config.
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*
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* @ops_id: property of operation directions.
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* @flip: property of mirror, flip.
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* @degree: property of rotation degree.
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* @fmt: property of image format.
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* @sz: property of image size.
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* @pos: property of image position(src-cropped,dst-scaler).
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*/
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struct drm_rockchip_ipp_config {
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enum drm_rockchip_ops_id ops_id;
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enum drm_rockchip_flip flip;
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enum drm_rockchip_degree degree;
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__u32 fmt;
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struct drm_rockchip_sz sz;
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struct drm_rockchip_pos pos;
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};
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enum drm_rockchip_ipp_cmd {
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IPP_CMD_NONE,
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IPP_CMD_M2M,
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IPP_CMD_WB,
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IPP_CMD_OUTPUT,
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IPP_CMD_MAX,
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};
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/**
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* A structure for ipp property.
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*
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* @config: source, destination config.
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* @cmd: definition of command.
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* @ipp_id: id of ipp driver.
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* @prop_id: id of property.
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* @refresh_rate: refresh rate.
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*/
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struct drm_rockchip_ipp_property {
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struct drm_rockchip_ipp_config config[ROCKCHIP_DRM_OPS_MAX];
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enum drm_rockchip_ipp_cmd cmd;
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__u32 ipp_id;
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__u32 prop_id;
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__u32 refresh_rate;
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};
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enum drm_rockchip_ipp_buf_type {
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IPP_BUF_ENQUEUE,
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IPP_BUF_DEQUEUE,
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};
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/**
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* A structure for ipp buffer operations.
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*
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* @ops_id: operation directions.
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* @buf_type: definition of buffer.
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* @prop_id: id of property.
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* @buf_id: id of buffer.
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* @handle: Y, Cb, Cr each planar handle.
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* @user_data: user data.
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*/
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struct drm_rockchip_ipp_queue_buf {
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enum drm_rockchip_ops_id ops_id;
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enum drm_rockchip_ipp_buf_type buf_type;
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__u32 prop_id;
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__u32 buf_id;
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__u32 handle[ROCKCHIP_DRM_PLANAR_MAX];
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__u32 reserved;
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__u64 user_data;
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};
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enum drm_rockchip_ipp_ctrl {
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IPP_CTRL_PLAY,
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IPP_CTRL_STOP,
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IPP_CTRL_PAUSE,
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IPP_CTRL_RESUME,
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IPP_CTRL_MAX,
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};
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/**
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* A structure for ipp start/stop operations.
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*
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* @prop_id: id of property.
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* @ctrl: definition of control.
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*/
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struct drm_rockchip_ipp_cmd_ctrl {
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__u32 prop_id;
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enum drm_rockchip_ipp_ctrl ctrl;
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};
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#define DRM_ROCKCHIP_GEM_CREATE 0x00
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#define DRM_ROCKCHIP_GEM_MAP_OFFSET 0x01
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#define DRM_ROCKCHIP_GEM_MMAP 0x02
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/* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
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#define DRM_ROCKCHIP_GEM_GET 0x04
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#define DRM_ROCKCHIP_VIDI_CONNECTION 0x07
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/* G2D */
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#define DRM_ROCKCHIP_G2D_GET_VER 0x20
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#define DRM_ROCKCHIP_G2D_SET_CMDLIST 0x21
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#define DRM_ROCKCHIP_G2D_EXEC 0x22
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/* IPP - Image Post Processing */
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#define DRM_ROCKCHIP_IPP_GET_PROPERTY 0x30
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#define DRM_ROCKCHIP_IPP_SET_PROPERTY 0x31
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#define DRM_ROCKCHIP_IPP_QUEUE_BUF 0x32
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#define DRM_ROCKCHIP_IPP_CMD_CTRL 0x33
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#define DRM_IOCTL_ROCKCHIP_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_ROCKCHIP_GEM_CREATE, struct drm_rockchip_gem_create)
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#define DRM_IOCTL_ROCKCHIP_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_ROCKCHIP_GEM_MAP_OFFSET, struct drm_rockchip_gem_map_off)
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#define DRM_IOCTL_ROCKCHIP_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_ROCKCHIP_GEM_MMAP, struct drm_rockchip_gem_mmap)
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#define DRM_IOCTL_ROCKCHIP_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_ROCKCHIP_GEM_GET, struct drm_rockchip_gem_info)
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#define DRM_IOCTL_ROCKCHIP_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_ROCKCHIP_VIDI_CONNECTION, struct drm_rockchip_vidi_connection)
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#define DRM_IOCTL_ROCKCHIP_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_ROCKCHIP_G2D_GET_VER, struct drm_rockchip_g2d_get_ver)
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#define DRM_IOCTL_ROCKCHIP_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_ROCKCHIP_G2D_SET_CMDLIST, struct drm_rockchip_g2d_set_cmdlist)
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#define DRM_IOCTL_ROCKCHIP_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_ROCKCHIP_G2D_EXEC, struct drm_rockchip_g2d_exec)
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#define DRM_IOCTL_ROCKCHIP_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_ROCKCHIP_IPP_GET_PROPERTY, struct drm_rockchip_ipp_prop_list)
|
||||
#define DRM_IOCTL_ROCKCHIP_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
|
||||
DRM_ROCKCHIP_IPP_SET_PROPERTY, struct drm_rockchip_ipp_property)
|
||||
#define DRM_IOCTL_ROCKCHIP_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + \
|
||||
DRM_ROCKCHIP_IPP_QUEUE_BUF, struct drm_rockchip_ipp_queue_buf)
|
||||
#define DRM_IOCTL_ROCKCHIP_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + \
|
||||
DRM_ROCKCHIP_IPP_CMD_CTRL, struct drm_rockchip_ipp_cmd_ctrl)
|
||||
|
||||
/* ROCKCHIP specific events */
|
||||
#define DRM_ROCKCHIP_G2D_EVENT 0x80000000
|
||||
#define DRM_ROCKCHIP_IPP_EVENT 0x80000001
|
||||
|
||||
struct drm_rockchip_g2d_event {
|
||||
struct drm_event base;
|
||||
__u64 user_data;
|
||||
__u32 tv_sec;
|
||||
__u32 tv_usec;
|
||||
__u32 cmdlist_no;
|
||||
__u32 reserved;
|
||||
};
|
||||
|
||||
struct drm_rockchip_ipp_event {
|
||||
struct drm_event base;
|
||||
__u64 user_data;
|
||||
__u32 tv_sec;
|
||||
__u32 tv_usec;
|
||||
__u32 prop_id;
|
||||
__u32 reserved;
|
||||
__u32 buf_id[ROCKCHIP_DRM_OPS_MAX];
|
||||
};
|
||||
|
||||
#endif /* _UAPI_ROCKCHIP_DRM_H_ */
|
||||
Loading…
Reference in New Issue
Block a user