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platform/x86/amd/pmc: Isolate STB code changes to a new file

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Since S2D (Spill to DRAM) uses different message port offsets compared to
PMC message offsets for communication with PMFW, relocate the S2D macros
from pmc.c to a new file, mp1_stb.c, for better code organization.

Following this change, it is logical to introduce a new structure,
"struct stb_arg," to pass the message, argument, and response offset
details to PMFW via the amd_pmc_send_cmd() call. Additionally, move the
s2d_msg_id member from amd_pmc_dev into the new structure.

Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Co-developed-by: Sanket Goswami <Sanket.Goswami@amd.com>
Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com>
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Link: https://lore.kernel.org/r/20241108070822.3912689-6-Shyam-sundar.S-k@amd.com
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
This commit is contained in:
Shyam Sundar S K 2024-11-08 12:38:17 +05:30 committed by Ilpo Järvinen
parent 2851f4f8ed
commit 3279f7a6b7
No known key found for this signature in database
GPG Key ID: 59AC4F6153E5CE31
3 changed files with 36 additions and 23 deletions
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33
drivers/platform/x86/amd/pmc/mp1_stb.c
View File

@ -31,6 +31,11 @@
#define STB_FORCE_FLUSH_DATA 0xCF
#define FIFO_SIZE 4096
/* STB S2D(Spill to DRAM) has different message port offset */
#define AMD_S2D_REGISTER_MESSAGE 0xA20
#define AMD_S2D_REGISTER_RESPONSE 0xA80
#define AMD_S2D_REGISTER_ARGUMENT 0xA88
static bool enable_stb;
module_param(enable_stb, bool, 0644);
MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism");
@ -170,7 +175,7 @@ static int amd_stb_debugfs_open_v2(struct inode *inode, struct file *filp)
return amd_stb_handle_efr(filp);
/* Get the num_samples to calculate the last push location */
ret = amd_pmc_send_cmd(dev, S2D_NUM_SAMPLES, &num_samples, dev->s2d_msg_id, true);
ret = amd_pmc_send_cmd(dev, S2D_NUM_SAMPLES, &num_samples, dev->stb_arg.s2d_msg_id, true);
/* Clear msg_port for other SMU operation */
dev->msg_port = MSG_PORT_PMC;
if (ret) {
@ -233,18 +238,24 @@ static bool amd_is_stb_supported(struct amd_pmc_dev *dev)
switch (dev->cpu_id) {
case AMD_CPU_ID_YC:
case AMD_CPU_ID_CB:
dev->s2d_msg_id = 0xBE;
return true;
dev->stb_arg.s2d_msg_id = 0xBE;
break;
case AMD_CPU_ID_PS:
dev->s2d_msg_id = 0x85;
return true;
dev->stb_arg.s2d_msg_id = 0x85;
break;
case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
dev->s2d_msg_id = 0xDE;
return true;
dev->stb_arg.s2d_msg_id = 0xDE;
break;
default:
return false;
}
dev->stb_arg.msg = AMD_S2D_REGISTER_MESSAGE;
dev->stb_arg.arg = AMD_S2D_REGISTER_ARGUMENT;
dev->stb_arg.resp = AMD_S2D_REGISTER_RESPONSE;
return true;
}
int amd_stb_s2d_init(struct amd_pmc_dev *dev)
@ -269,18 +280,18 @@ int amd_stb_s2d_init(struct amd_pmc_dev *dev)
/* Spill to DRAM feature uses separate SMU message port */
dev->msg_port = MSG_PORT_S2D;
amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, dev->s2d_msg_id, true);
amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, dev->stb_arg.s2d_msg_id, true);
if (size != S2D_TELEMETRY_BYTES_MAX)
return -EIO;
/* Get DRAM size */
ret = amd_pmc_send_cmd(dev, S2D_DRAM_SIZE, &dev->dram_size, dev->s2d_msg_id, true);
ret = amd_pmc_send_cmd(dev, S2D_DRAM_SIZE, &dev->dram_size, dev->stb_arg.s2d_msg_id, true);
if (ret || !dev->dram_size)
dev->dram_size = S2D_TELEMETRY_DRAMBYTES_MAX;
/* Get STB DRAM address */
amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, dev->s2d_msg_id, true);
amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, dev->s2d_msg_id, true);
amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, dev->stb_arg.s2d_msg_id, true);
amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, dev->stb_arg.s2d_msg_id, true);
stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);

17
drivers/platform/x86/amd/pmc/pmc.c
View File

@ -44,11 +44,6 @@
#define AMD_PMC_STB_S2IDLE_RESTORE 0xC6000002
#define AMD_PMC_STB_S2IDLE_CHECK 0xC6000003
/* STB S2D(Spill to DRAM) has different message port offset */
#define AMD_S2D_REGISTER_MESSAGE 0xA20
#define AMD_S2D_REGISTER_RESPONSE 0xA80
#define AMD_S2D_REGISTER_ARGUMENT 0xA88
/* Base address of SMU for mapping physical address to virtual address */
#define AMD_PMC_MAPPING_SIZE 0x01000
#define AMD_PMC_BASE_ADDR_OFFSET 0x10000
@ -466,9 +461,9 @@ static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
u32 value, message, argument, response;
if (dev->msg_port == MSG_PORT_S2D) {
message = AMD_S2D_REGISTER_MESSAGE;
argument = AMD_S2D_REGISTER_ARGUMENT;
response = AMD_S2D_REGISTER_RESPONSE;
message = dev->stb_arg.msg;
argument = dev->stb_arg.arg;
response = dev->stb_arg.resp;
} else {
message = dev->smu_msg;
argument = AMD_PMC_REGISTER_ARGUMENT;
@ -493,9 +488,9 @@ int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool r
mutex_lock(&dev->lock);
if (dev->msg_port == MSG_PORT_S2D) {
message = AMD_S2D_REGISTER_MESSAGE;
argument = AMD_S2D_REGISTER_ARGUMENT;
response = AMD_S2D_REGISTER_RESPONSE;
message = dev->stb_arg.msg;
argument = dev->stb_arg.arg;
response = dev->stb_arg.resp;
} else {
message = dev->smu_msg;
argument = AMD_PMC_REGISTER_ARGUMENT;

9
drivers/platform/x86/amd/pmc/pmc.h
View File

@ -30,6 +30,13 @@ struct amd_mp2_dev {
bool is_stb_data;
};
struct stb_arg {
u32 s2d_msg_id;
u32 msg;
u32 arg;
u32 resp;
};
struct amd_pmc_dev {
void __iomem *regbase;
void __iomem *smu_virt_addr;
@ -40,7 +47,6 @@ struct amd_pmc_dev {
u32 active_ips;
u32 dram_size;
u32 num_ips;
u32 s2d_msg_id;
u32 smu_msg;
/* SMU version information */
u8 smu_program;
@ -55,6 +61,7 @@ struct amd_pmc_dev {
struct quirk_entry *quirks;
bool disable_8042_wakeup;
struct amd_mp2_dev *mp2;
struct stb_arg stb_arg;
};
void amd_pmc_process_restore_quirks(struct amd_pmc_dev *dev);