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arm64: dts: qcom: sm6115: Add i2c/spi nodes
Add I2C/SPI nodes for SM6115. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221130200950.144618-11-a39.skl@gmail.com
This commit is contained in:
Adam Skladowski
Bjorn Andersson
parent
1586c57935
commit
323647d32e
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@ -6,6 +6,7 @@
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#include <dt-bindings/clock/qcom,gcc-sm6115.h>
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#include <dt-bindings/clock/qcom,sm6115-dispcc.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/dma/qcom-gpi.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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@ -365,6 +366,90 @@ tlmm: pinctrl@500000 {
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interrupt-controller;
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#interrupt-cells = <2>;
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qup_i2c0_default: qup-i2c0-default-state {
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pins = "gpio0", "gpio1";
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function = "qup0";
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drive-strength = <2>;
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bias-pull-up;
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};
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qup_i2c1_default: qup-i2c1-default-state {
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pins = "gpio4", "gpio5";
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function = "qup1";
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drive-strength = <2>;
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bias-pull-up;
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};
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qup_i2c2_default: qup-i2c2-default-state {
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pins = "gpio6", "gpio7";
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function = "qup2";
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drive-strength = <2>;
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bias-pull-up;
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};
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qup_i2c3_default: qup-i2c3-default-state {
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pins = "gpio8", "gpio9";
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function = "qup3";
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drive-strength = <2>;
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bias-pull-up;
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};
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qup_i2c4_default: qup-i2c4-default-state {
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pins = "gpio12", "gpio13";
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function = "qup4";
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drive-strength = <2>;
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bias-pull-up;
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};
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qup_i2c5_default: qup-i2c5-default-state {
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pins = "gpio14", "gpio15";
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function = "qup5";
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drive-strength = <2>;
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bias-pull-up;
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};
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qup_spi0_default: qup-spi0-default-state {
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pins = "gpio0", "gpio1","gpio2", "gpio3";
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function = "qup0";
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drive-strength = <2>;
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bias-pull-up;
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};
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qup_spi1_default: qup-spi1-default-state {
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pins = "gpio4", "gpio5", "gpio69", "gpio70";
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function = "qup1";
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drive-strength = <2>;
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bias-pull-up;
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};
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qup_spi2_default: qup-spi2-default-state {
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pins = "gpio6", "gpio7", "gpio71", "gpio80";
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function = "qup2";
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drive-strength = <2>;
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bias-pull-up;
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};
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qup_spi3_default: qup-spi3-default-state {
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pins = "gpio8", "gpio9", "gpio10", "gpio11";
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function = "qup3";
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drive-strength = <2>;
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bias-pull-up;
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};
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qup_spi4_default: qup-spi4-default-state {
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pins = "gpio12", "gpio13", "gpio96", "gpio97";
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function = "qup4";
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drive-strength = <2>;
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bias-pull-up;
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};
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qup_spi5_default: qup-spi5-default-state {
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pins = "gpio14", "gpio15", "gpio16", "gpio17";
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function = "qup5";
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drive-strength = <2>;
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bias-pull-up;
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};
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sdc1_state_on: sdc1-on-state {
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clk-pins {
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pins = "sdc1_clk";
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@ -701,6 +786,211 @@ gpi_dma0: dma-controller@4a00000 {
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status = "disabled";
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};
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qupv3_id_0: geniqup@4ac0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x04ac0000 0x2000>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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#address-cells = <1>;
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#size-cells = <1>;
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iommus = <&apps_smmu 0xe3 0x0>;
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ranges;
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status = "disabled";
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i2c0: i2c@4a80000 {
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compatible = "qcom,geni-i2c";
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reg = <0x04a80000 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c0_default>;
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interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
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<&gpi_dma0 1 0 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi0: spi@4a80000 {
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compatible = "qcom,geni-spi";
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reg = <0x04a80000 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_spi0_default>;
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interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
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<&gpi_dma0 1 0 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@4a84000 {
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compatible = "qcom,geni-i2c";
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reg = <0x04a84000 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c1_default>;
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interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
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<&gpi_dma0 1 1 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi1: spi@4a84000 {
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compatible = "qcom,geni-spi";
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reg = <0x04a84000 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_spi1_default>;
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interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
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<&gpi_dma0 1 1 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@4a88000 {
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compatible = "qcom,geni-i2c";
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reg = <0x04a88000 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c2_default>;
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interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
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<&gpi_dma0 1 2 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi2: spi@4a88000 {
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compatible = "qcom,geni-spi";
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reg = <0x04a88000 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_spi2_default>;
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interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
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<&gpi_dma0 1 2 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c3: i2c@4a8c000 {
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compatible = "qcom,geni-i2c";
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reg = <0x04a8c000 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c3_default>;
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interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
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<&gpi_dma0 1 3 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi3: spi@4a8c000 {
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compatible = "qcom,geni-spi";
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reg = <0x04a8c000 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_spi3_default>;
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interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
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<&gpi_dma0 1 3 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c4: i2c@4a90000 {
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compatible = "qcom,geni-i2c";
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reg = <0x04a90000 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c4_default>;
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interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
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<&gpi_dma0 1 4 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi4: spi@4a90000 {
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compatible = "qcom,geni-spi";
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reg = <0x04a90000 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_spi4_default>;
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interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
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<&gpi_dma0 1 4 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c5: i2c@4a94000 {
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compatible = "qcom,geni-i2c";
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reg = <0x04a94000 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c5_default>;
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interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
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<&gpi_dma0 1 5 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi5: spi@4a94000 {
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compatible = "qcom,geni-spi";
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reg = <0x04a94000 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_spi5_default>;
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interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
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<&gpi_dma0 1 5 QCOM_GPI_SPI>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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usb_1: usb@4ef8800 {
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compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
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reg = <0x04ef8800 0x400>;
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