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media: platform: qcom/iris: introduce optional controller_rst_tbl

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Introduce an optional controller_rst_tbl use to store reset lines
used to reset part of the controller.

This is necessary for the vpu3 support, when the xo reset line
must be asserted separately from the other reset line
on power off operation.

Factor the iris_init_resets() logic to allow requesting
multiple reset tables.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> # x1e Dell
Reviewed-by: Dikshita Agarwal <quic_dikshita@quicinc.com>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Vikash Garodia <quic_vgarodia@quicinc.com>
Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
This commit is contained in:
Neil Armstrong 2025-04-17 16:59:03 +02:00 committed by Hans Verkuil
parent c69df5de4a
commit 322e9061ed
3 changed files with 31 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/media/platform/qcom/iris/iris_core.h
View File

@ -43,6 +43,7 @@ struct icc_info {
* @clock_tbl: table of iris clocks
* @clk_count: count of iris clocks
* @resets: table of iris reset clocks
* @controller_resets: table of controller reset clocks
* @iris_platform_data: a structure for platform data
* @state: current state of core
* @iface_q_table_daddr: device address for interface queue table memory
@ -82,6 +83,7 @@ struct iris_core {
struct clk_bulk_data *clock_tbl;
u32 clk_count;
struct reset_control_bulk_data *resets;
struct reset_control_bulk_data *controller_resets;
const struct iris_platform_data *iris_platform_data;
enum iris_core_state state;
dma_addr_t iface_q_table_daddr;

2
drivers/media/platform/qcom/iris/iris_platform_common.h
View File

@ -156,6 +156,8 @@ struct iris_platform_data {
unsigned int clk_tbl_size;
const char * const *clk_rst_tbl;
unsigned int clk_rst_tbl_size;
const char * const *controller_rst_tbl;
unsigned int controller_rst_tbl_size;
u64 dma_mask;
const char *fwname;
u32 pas_id;

39
drivers/media/platform/qcom/iris/iris_probe.c
View File

@ -91,25 +91,40 @@ static int iris_init_clocks(struct iris_core *core)
return 0;
}
static int iris_init_resets(struct iris_core *core)
static int iris_init_reset_table(struct iris_core *core,
struct reset_control_bulk_data **resets,
const char * const *rst_tbl, u32 rst_tbl_size)
{
const char * const *rst_tbl;
u32 rst_tbl_size;
u32 i = 0;
rst_tbl = core->iris_platform_data->clk_rst_tbl;
rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size;
core->resets = devm_kzalloc(core->dev,
sizeof(*core->resets) * rst_tbl_size,
GFP_KERNEL);
if (!core->resets)
*resets = devm_kzalloc(core->dev,
sizeof(struct reset_control_bulk_data) * rst_tbl_size,
GFP_KERNEL);
if (!*resets)
return -ENOMEM;
for (i = 0; i < rst_tbl_size; i++)
core->resets[i].id = rst_tbl[i];
(*resets)[i].id = rst_tbl[i];
return devm_reset_control_bulk_get_exclusive(core->dev, rst_tbl_size, core->resets);
return devm_reset_control_bulk_get_exclusive(core->dev, rst_tbl_size, *resets);
}
static int iris_init_resets(struct iris_core *core)
{
int ret;
ret = iris_init_reset_table(core, &core->resets,
core->iris_platform_data->clk_rst_tbl,
core->iris_platform_data->clk_rst_tbl_size);
if (ret)
return ret;
if (!core->iris_platform_data->controller_rst_tbl_size)
return 0;
return iris_init_reset_table(core, &core->controller_resets,
core->iris_platform_data->controller_rst_tbl,
core->iris_platform_data->controller_rst_tbl_size);
}
static int iris_init_resources(struct iris_core *core)