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drm/xe/migrate: Populate struct drm_pagemap_addr array
Workaround to ensure all addresses are populated in the array as this is expected when creating the copy batch. This is required because the migrate layer does not support 2MB GPU pages yet. A proper fix will come in a follow-up. Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://lore.kernel.org/r/20250805140028.599361-6-francois.dugast@intel.com Signed-off-by: Francois Dugast <francois.dugast@intel.com>
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@ -1802,6 +1802,7 @@ static struct dma_fence *xe_migrate_vram(struct xe_migrate *m,
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unsigned int pitch = len >= PAGE_SIZE && !(len & ~PAGE_MASK) ?
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PAGE_SIZE : 4;
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int err;
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unsigned long i, j;
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if (drm_WARN_ON(&xe->drm, (len & XE_CACHELINE_MASK) ||
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(sram_offset | vram_addr) & XE_CACHELINE_MASK))
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@ -1818,6 +1819,24 @@ static struct dma_fence *xe_migrate_vram(struct xe_migrate *m,
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return ERR_PTR(err);
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}
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/*
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* If the order of a struct drm_pagemap_addr entry is greater than 0,
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* the entry is populated by GPU pagemap but subsequent entries within
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* the range of that order are not populated.
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* build_pt_update_batch_sram() expects a fully populated array of
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* struct drm_pagemap_addr. Ensure this is the case even with higher
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* orders.
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*/
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for (i = 0; i < npages;) {
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unsigned int order = sram_addr[i].order;
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for (j = 1; j < NR_PAGES(order) && i + j < npages; j++)
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if (!sram_addr[i + j].addr)
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sram_addr[i + j].addr = sram_addr[i].addr + j * PAGE_SIZE;
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i += NR_PAGES(order);
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}
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build_pt_update_batch_sram(m, bb, pt_slot * XE_PAGE_SIZE,
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sram_addr, len + sram_offset);
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