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dt-bindings: pinctrl: mediatek: Correct indentation and style in DTS example
DTS example in the bindings should be indented with 2- or 4-spaces and aligned with opening '- |', so correct any differences like 3-spaces or mixtures 2- and 4-spaces in one binding. No functional changes here, but saves some comments during reviews of new patches built on existing code. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/20250324125105.81774-2-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Krzysztof Kozlowski
Linus Walleij
parent
5d7c4697b0
commit
31d820fe42
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@ -137,64 +137,43 @@ examples:
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#size-cells = <2>;
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pinctrl@1c20800 {
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compatible = "mediatek,mt8135-pinctrl";
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reg = <0 0x1000B000 0 0x1000>;
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mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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compatible = "mediatek,mt8135-pinctrl";
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reg = <0 0x1000B000 0 0x1000>;
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mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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i2c0_pins_a: i2c0-pins {
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pins1 {
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pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
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<MT8135_PIN_101_SCL0__FUNC_SCL0>;
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bias-disable;
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};
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};
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i2c1_pins_a: i2c1-pins {
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pins {
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pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
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<MT8135_PIN_196_SCL1__FUNC_SCL1>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
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};
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};
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i2c2_pins_a: i2c2-pins {
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pins1 {
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pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
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bias-pull-down;
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i2c0_pins_a: i2c0-pins {
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pins1 {
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pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
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<MT8135_PIN_101_SCL0__FUNC_SCL0>;
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bias-disable;
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};
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};
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pins2 {
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pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
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bias-pull-up;
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};
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};
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i2c3_pins_a: i2c3-pins {
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pins1 {
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pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
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<MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
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i2c1_pins_a: i2c1-pins {
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pins {
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pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
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<MT8135_PIN_196_SCL1__FUNC_SCL1>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
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};
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};
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pins2 {
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pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
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<MT8135_PIN_36_SDA3__FUNC_SDA3>;
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output-low;
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bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
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};
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i2c2_pins_a: i2c2-pins {
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pins1 {
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pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
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bias-pull-down;
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};
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pins3 {
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pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
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<MT8135_PIN_60_JTDI__FUNC_JTDI>;
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drive-strength = <32>;
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pins2 {
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pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
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bias-pull-up;
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};
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};
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};
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};
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};
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@ -366,34 +366,34 @@ examples:
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#size-cells = <2>;
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pio: pinctrl@10211000 {
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compatible = "mediatek,mt7622-pinctrl";
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reg = <0 0x10211000 0 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "mediatek,mt7622-pinctrl";
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reg = <0 0x10211000 0 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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pinctrl_eth_default: eth-pins {
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mux-mdio {
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groups = "mdc_mdio";
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function = "eth";
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drive-strength = <12>;
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};
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pinctrl_eth_default: eth-pins {
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mux-mdio {
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groups = "mdc_mdio";
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function = "eth";
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drive-strength = <12>;
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};
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mux-gmac2 {
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groups = "rgmii_via_gmac2";
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function = "eth";
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drive-strength = <12>;
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};
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mux-gmac2 {
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groups = "rgmii_via_gmac2";
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function = "eth";
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drive-strength = <12>;
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};
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mux-esw {
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groups = "esw";
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function = "eth";
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drive-strength = <8>;
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};
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mux-esw {
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groups = "esw";
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function = "eth";
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drive-strength = <8>;
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};
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conf-mdio {
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pins = "MDC";
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bias-pull-up;
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conf-mdio {
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pins = "MDC";
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bias-pull-up;
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};
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};
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};
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};
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};
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@ -195,43 +195,43 @@ examples:
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#size-cells = <2>;
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pio: pinctrl@10005000 {
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compatible = "mediatek,mt8183-pinctrl";
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reg = <0 0x10005000 0 0x1000>,
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<0 0x11f20000 0 0x1000>,
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<0 0x11e80000 0 0x1000>,
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<0 0x11e70000 0 0x1000>,
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<0 0x11e90000 0 0x1000>,
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<0 0x11d30000 0 0x1000>,
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<0 0x11d20000 0 0x1000>,
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<0 0x11c50000 0 0x1000>,
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<0 0x11f30000 0 0x1000>,
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<0 0x1000b000 0 0x1000>;
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reg-names = "iocfg0", "iocfg1", "iocfg2",
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"iocfg3", "iocfg4", "iocfg5",
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"iocfg6", "iocfg7", "iocfg8",
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"eint";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pio 0 0 192>;
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interrupt-controller;
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interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <2>;
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compatible = "mediatek,mt8183-pinctrl";
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reg = <0 0x10005000 0 0x1000>,
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<0 0x11f20000 0 0x1000>,
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<0 0x11e80000 0 0x1000>,
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<0 0x11e70000 0 0x1000>,
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<0 0x11e90000 0 0x1000>,
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<0 0x11d30000 0 0x1000>,
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<0 0x11d20000 0 0x1000>,
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<0 0x11c50000 0 0x1000>,
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<0 0x11f30000 0 0x1000>,
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<0 0x1000b000 0 0x1000>;
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reg-names = "iocfg0", "iocfg1", "iocfg2",
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"iocfg3", "iocfg4", "iocfg5",
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"iocfg6", "iocfg7", "iocfg8",
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"eint";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pio 0 0 192>;
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interrupt-controller;
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interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <2>;
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i2c0_pins_a: i2c0-pins {
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pins1 {
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pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
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<PINMUX_GPIO49__FUNC_SDA5>;
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mediatek,pull-up-adv = <3>;
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drive-strength-microamp = <1000>;
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i2c0_pins_a: i2c0-pins {
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pins1 {
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pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
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<PINMUX_GPIO49__FUNC_SDA5>;
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mediatek,pull-up-adv = <3>;
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drive-strength-microamp = <1000>;
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};
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};
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};
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i2c1_pins_a: i2c1-pins {
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pins {
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pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
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<PINMUX_GPIO51__FUNC_SDA3>;
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mediatek,pull-down-adv = <2>;
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i2c1_pins_a: i2c1-pins {
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pins {
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pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
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<PINMUX_GPIO51__FUNC_SDA3>;
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mediatek,pull-down-adv = <2>;
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};
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};
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};
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};
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};
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@ -142,43 +142,43 @@ additionalProperties: false
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examples:
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- |
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#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pio: pinctrl@10005000 {
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compatible = "mediatek,mt8192-pinctrl";
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reg = <0x10005000 0x1000>,
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<0x11c20000 0x1000>,
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<0x11d10000 0x1000>,
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<0x11d30000 0x1000>,
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<0x11d40000 0x1000>,
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<0x11e20000 0x1000>,
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<0x11e70000 0x1000>,
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<0x11ea0000 0x1000>,
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<0x11f20000 0x1000>,
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<0x11f30000 0x1000>,
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<0x1000b000 0x1000>;
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reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
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"iocfg_bl", "iocfg_br", "iocfg_lm",
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"iocfg_lb", "iocfg_rt", "iocfg_lt",
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"iocfg_tl", "eint";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pio 0 0 220>;
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interrupt-controller;
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interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
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#interrupt-cells = <2>;
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#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pio: pinctrl@10005000 {
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compatible = "mediatek,mt8192-pinctrl";
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reg = <0x10005000 0x1000>,
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<0x11c20000 0x1000>,
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<0x11d10000 0x1000>,
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<0x11d30000 0x1000>,
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<0x11d40000 0x1000>,
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<0x11e20000 0x1000>,
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<0x11e70000 0x1000>,
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<0x11ea0000 0x1000>,
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<0x11f20000 0x1000>,
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<0x11f30000 0x1000>,
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<0x1000b000 0x1000>;
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reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
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"iocfg_bl", "iocfg_br", "iocfg_lm",
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"iocfg_lb", "iocfg_rt", "iocfg_lt",
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"iocfg_tl", "eint";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pio 0 0 220>;
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interrupt-controller;
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interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
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#interrupt-cells = <2>;
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spi1-default-pins {
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pins-cs-mosi-clk {
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pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,
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<PINMUX_GPIO159__FUNC_SPI1_A_MO>,
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<PINMUX_GPIO156__FUNC_SPI1_A_CLK>;
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bias-disable;
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};
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pins-miso {
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pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>;
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bias-pull-down;
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};
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};
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spi1-default-pins {
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pins-cs-mosi-clk {
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pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,
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<PINMUX_GPIO159__FUNC_SPI1_A_MO>,
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<PINMUX_GPIO156__FUNC_SPI1_A_CLK>;
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bias-disable;
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};
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pins-miso {
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pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>;
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bias-pull-down;
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};
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};
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};
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