perf vendor events: Update EmeraldRapids events

Update events from v1.11 to v1.14.

Bring in the event updates v1.14:
6f6e4c8c90
e363f82276

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Link: https://lore.kernel.org/r/20250630163101.1920170-6-irogers@google.com
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
This commit is contained in:
Ian Rogers 2025-06-30 09:30:50 -07:00 committed by Namhyung Kim
parent 73a3365689
commit 31c8714cf5
4 changed files with 34 additions and 2 deletions

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@ -684,7 +684,7 @@
"Counter": "0,1,2,3",
"EventCode": "0x4c",
"EventName": "LOAD_HIT_PREFETCH.SWPF",
"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions. Available PDIST counters: 0",
"PublicDescription": "Counts all software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions. Available PDIST counters: 0",
"SampleAfterValue": "100003",
"UMask": "0x1"
},

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@ -1821,6 +1821,18 @@
"UMask": "0x4",
"Unit": "IIO"
},
{
"BriefDescription": "Posted requests sent by the integrated IO (IIO) controller to the Ubox, useful for counting message signaled interrupts (MSI).",
"Counter": "0,1,2,3",
"EventCode": "0x8e",
"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX_POSTED",
"Experimental": "1",
"FCMask": "0x01",
"PerPkg": "1",
"PortMask": "0x00FF",
"UMask": "0x4",
"Unit": "IIO"
},
{
"BriefDescription": "ITC address map 1",
"Counter": "0,1,2,3",

View File

@ -2145,6 +2145,16 @@
"UMask": "0x1",
"Unit": "MCHBM"
},
{
"BriefDescription": "ECC Correctable Errors",
"Counter": "0,1,2,3",
"EventCode": "0x09",
"EventName": "UNC_MCHBM_ECC_CORRECTABLE_ERRORS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ECC Correctable Errors. Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit errors in lockstep mode.",
"Unit": "MCHBM"
},
{
"BriefDescription": "HBM Precharge All Commands",
"Counter": "0,1,2,3",
@ -2759,6 +2769,16 @@
"UMask": "0x3",
"Unit": "iMC"
},
{
"BriefDescription": "ECC Correctable Errors",
"Counter": "0,1,2,3",
"EventCode": "0x09",
"EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
"Experimental": "1",
"PerPkg": "1",
"PublicDescription": "ECC Correctable Errors : Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit errors in lockstep mode.",
"Unit": "iMC"
},
{
"BriefDescription": "IMC Clockticks at HCLK frequency",
"Counter": "0,1,2,3",

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@ -9,7 +9,7 @@ GenuineIntel-6-4F,v23,broadwellx,core
GenuineIntel-6-55-[56789ABCDEF],v1.25,cascadelakex,core
GenuineIntel-6-DD,v1.00,clearwaterforest,core
GenuineIntel-6-9[6C],v1.05,elkhartlake,core
GenuineIntel-6-CF,v1.11,emeraldrapids,core
GenuineIntel-6-CF,v1.14,emeraldrapids,core
GenuineIntel-6-5[CF],v13,goldmont,core
GenuineIntel-6-7A,v1.01,goldmontplus,core
GenuineIntel-6-B6,v1.07,grandridge,core

1 Family-model Version Filename EventType
9 GenuineIntel-6-55-[56789ABCDEF] v1.25 cascadelakex core
10 GenuineIntel-6-DD v1.00 clearwaterforest core
11 GenuineIntel-6-9[6C] v1.05 elkhartlake core
12 GenuineIntel-6-CF v1.11 v1.14 emeraldrapids core
13 GenuineIntel-6-5[CF] v13 goldmont core
14 GenuineIntel-6-7A v1.01 goldmontplus core
15 GenuineIntel-6-B6 v1.07 grandridge core