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perf vendor events: Update EmeraldRapids events
Update events from v1.11 to v1.14. Bring in the event updates v1.14:6f6e4c8c90e363f82276Signed-off-by: Ian Rogers <irogers@google.com> Tested-by: Thomas Falcon <thomas.falcon@intel.com> Link: https://lore.kernel.org/r/20250630163101.1920170-6-irogers@google.com Signed-off-by: Namhyung Kim <namhyung@kernel.org>
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@ -684,7 +684,7 @@
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"Counter": "0,1,2,3",
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"EventCode": "0x4c",
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"EventName": "LOAD_HIT_PREFETCH.SWPF",
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"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions. Available PDIST counters: 0",
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"PublicDescription": "Counts all software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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@ -1821,6 +1821,18 @@
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"UMask": "0x4",
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"Unit": "IIO"
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},
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{
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"BriefDescription": "Posted requests sent by the integrated IO (IIO) controller to the Ubox, useful for counting message signaled interrupts (MSI).",
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"Counter": "0,1,2,3",
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"EventCode": "0x8e",
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"EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX_POSTED",
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"Experimental": "1",
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"FCMask": "0x01",
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"PerPkg": "1",
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"PortMask": "0x00FF",
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"UMask": "0x4",
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"Unit": "IIO"
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},
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{
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"BriefDescription": "ITC address map 1",
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"Counter": "0,1,2,3",
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@ -2145,6 +2145,16 @@
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"UMask": "0x1",
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"Unit": "MCHBM"
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},
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{
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"BriefDescription": "ECC Correctable Errors",
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"Counter": "0,1,2,3",
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"EventCode": "0x09",
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"EventName": "UNC_MCHBM_ECC_CORRECTABLE_ERRORS",
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"Experimental": "1",
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"PerPkg": "1",
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"PublicDescription": "ECC Correctable Errors. Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit errors in lockstep mode.",
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"Unit": "MCHBM"
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},
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{
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"BriefDescription": "HBM Precharge All Commands",
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"Counter": "0,1,2,3",
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@ -2759,6 +2769,16 @@
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"UMask": "0x3",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "ECC Correctable Errors",
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"Counter": "0,1,2,3",
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"EventCode": "0x09",
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"EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
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"Experimental": "1",
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"PerPkg": "1",
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"PublicDescription": "ECC Correctable Errors : Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit errors in lockstep mode.",
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"Unit": "iMC"
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},
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{
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"BriefDescription": "IMC Clockticks at HCLK frequency",
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"Counter": "0,1,2,3",
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@ -9,7 +9,7 @@ GenuineIntel-6-4F,v23,broadwellx,core
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GenuineIntel-6-55-[56789ABCDEF],v1.25,cascadelakex,core
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GenuineIntel-6-DD,v1.00,clearwaterforest,core
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GenuineIntel-6-9[6C],v1.05,elkhartlake,core
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GenuineIntel-6-CF,v1.11,emeraldrapids,core
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GenuineIntel-6-CF,v1.14,emeraldrapids,core
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GenuineIntel-6-5[CF],v13,goldmont,core
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GenuineIntel-6-7A,v1.01,goldmontplus,core
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GenuineIntel-6-B6,v1.07,grandridge,core
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