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ARM: dts: qcom: adjust whitespace around '='

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Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment.  No functional
changes (same DTB).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220526204248.832139-2-krzysztof.kozlowski@linaro.org
This commit is contained in:
Krzysztof Kozlowski 2022-05-26 22:42:48 +02:00 committed by Bjorn Andersson
parent 7afef282d7
commit 31b2edcab4
9 changed files with 192 additions and 192 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
View File

@ -24,9 +24,9 @@ reserved-memory {
ramoops@88d00000{
compatible = "ramoops";
reg = <0x88d00000 0x100000>;
record-size = <0x00020000>;
console-size = <0x00020000>;
ftrace-size = <0x00020000>;
record-size = <0x00020000>;
console-size = <0x00020000>;
ftrace-size = <0x00020000>;
};
};
@ -98,8 +98,8 @@ s3 {
* tabla2x-slim-VDDIO_CDC
*/
s4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
qcom,switch-mode-frequency = <3200000>;
regulator-always-on;
};
@ -349,9 +349,9 @@ reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x65c>;
mode-normal = <0x77665501>;
mode-bootloader = <0x77665500>;
mode-recovery = <0x77665502>;
mode-normal = <0x77665501>;
mode-bootloader = <0x77665500>;
mode-recovery = <0x77665502>;
};
};
};

10
arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts
View File

@ -82,8 +82,8 @@ s3 {
};
s4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
qcom,switch-mode-frequency = <3200000>;
};
@ -230,9 +230,9 @@ sdcc1: mmc@12400000 {
sdcc3: mmc@12180000 {
status = "okay";
vmmc-supply = <&v3p3_fixed>;
pinctrl-names = "default";
pinctrl-0 = <&card_detect>;
cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&card_detect>;
cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>;
};
/* WLAN */
sdcc4: mmc@121c0000 {

14
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
View File

@ -108,8 +108,8 @@ s3 {
};
s4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
qcom,switch-mode-frequency = <3200000>;
};
@ -240,8 +240,8 @@ sata_phy0: phy@1b400000 {
};
sata0: sata@29000000 {
status = "okay";
target-supply = <&pm8921_s4>;
status = "okay";
target-supply = <&pm8921_s4>;
};
/* OTG */
@ -324,9 +324,9 @@ sdcc1: mmc@12400000 {
sdcc3: mmc@12180000 {
status = "okay";
vmmc-supply = <&pm8921_l6>;
pinctrl-names = "default";
pinctrl-0 = <&card_detect>;
cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&card_detect>;
cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>;
};
/* WLAN */
sdcc4: mmc@121c0000 {

136
arch/arm/boot/dts/qcom-apq8064.dtsi
View File

@ -430,8 +430,8 @@ saw3: power-controller@20b9000 {
};
sps_sic_non_secure: sps-sic-non-secure@12100000 {
compatible = "syscon";
reg = <0x12100000 0x10000>;
compatible = "syscon";
reg = <0x12100000 0x10000>;
};
gsbi1: gsbi@12440000 {
@ -836,22 +836,22 @@ mmcc: clock-controller@4000000 {
};
l2cc: clock-controller@2011000 {
compatible = "qcom,kpss-gcc", "syscon";
reg = <0x2011000 0x1000>;
compatible = "qcom,kpss-gcc", "syscon";
reg = <0x2011000 0x1000>;
};
rpm@108000 {
compatible = "qcom,rpm-apq8064";
reg = <0x108000 0x1000>;
qcom,ipc = <&l2cc 0x8 2>;
compatible = "qcom,rpm-apq8064";
reg = <0x108000 0x1000>;
qcom,ipc = <&l2cc 0x8 2>;
interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ack", "err", "wakeup";
interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ack", "err", "wakeup";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
#clock-cells = <1>;
};
@ -1004,39 +1004,39 @@ usb_hs4_phy: phy {
};
sata_phy0: phy@1b400000 {
compatible = "qcom,apq8064-sata-phy";
status = "disabled";
reg = <0x1b400000 0x200>;
reg-names = "phy_mem";
clocks = <&gcc SATA_PHY_CFG_CLK>;
clock-names = "cfg";
#phy-cells = <0>;
compatible = "qcom,apq8064-sata-phy";
status = "disabled";
reg = <0x1b400000 0x200>;
reg-names = "phy_mem";
clocks = <&gcc SATA_PHY_CFG_CLK>;
clock-names = "cfg";
#phy-cells = <0>;
};
sata0: sata@29000000 {
compatible = "qcom,apq8064-ahci", "generic-ahci";
status = "disabled";
reg = <0x29000000 0x180>;
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
compatible = "qcom,apq8064-ahci", "generic-ahci";
status = "disabled";
reg = <0x29000000 0x180>;
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SFAB_SATA_S_H_CLK>,
<&gcc SATA_H_CLK>,
<&gcc SATA_A_CLK>,
<&gcc SATA_RXOOB_CLK>,
<&gcc SATA_PMALIVE_CLK>;
clock-names = "slave_iface",
"iface",
"bus",
"rxoob",
"core_pmalive";
clocks = <&gcc SFAB_SATA_S_H_CLK>,
<&gcc SATA_H_CLK>,
<&gcc SATA_A_CLK>,
<&gcc SATA_RXOOB_CLK>,
<&gcc SATA_PMALIVE_CLK>;
clock-names = "slave_iface",
"iface",
"bus",
"rxoob",
"core_pmalive";
assigned-clocks = <&gcc SATA_RXOOB_CLK>,
<&gcc SATA_PMALIVE_CLK>;
assigned-clock-rates = <100000000>, <100000000>;
assigned-clocks = <&gcc SATA_RXOOB_CLK>,
<&gcc SATA_PMALIVE_CLK>;
assigned-clock-rates = <100000000>, <100000000>;
phys = <&sata_phy0>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
phys = <&sata_phy0>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
};
/* Temporary fixed regulator */
@ -1076,18 +1076,18 @@ amba {
#size-cells = <1>;
ranges;
sdcc1: mmc@12400000 {
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
pinctrl-names = "default";
pinctrl-0 = <&sdcc1_pins>;
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
pinctrl-names = "default";
pinctrl-0 = <&sdcc1_pins>;
arm,primecell-periphid = <0x00051180>;
reg = <0x12400000 0x2000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <8>;
max-frequency = <96000000>;
reg = <0x12400000 0x2000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <8>;
max-frequency = <96000000>;
non-removable;
cap-sd-highspeed;
cap-mmc-highspeed;
@ -1096,36 +1096,36 @@ sdcc1: mmc@12400000 {
};
sdcc3: mmc@12180000 {
compatible = "arm,pl18x", "arm,primecell";
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
status = "disabled";
reg = <0x12180000 0x2000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <4>;
status = "disabled";
reg = <0x12180000 0x2000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <4>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <192000000>;
max-frequency = <192000000>;
no-1-8-v;
dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
dma-names = "tx", "rx";
};
sdcc4: mmc@121c0000 {
compatible = "arm,pl18x", "arm,primecell";
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
status = "disabled";
reg = <0x121c0000 0x2000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <4>;
status = "disabled";
reg = <0x121c0000 0x2000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <4>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <48000000>;
max-frequency = <48000000>;
dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
dma-names = "tx", "rx";
pinctrl-names = "default";

32
arch/arm/boot/dts/qcom-ipq8064.dtsi
View File

@ -1184,16 +1184,16 @@ amba: amba {
ranges;
sdcc1: mmc@12400000 {
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
reg = <0x12400000 0x2000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x12400000 0x2000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <8>;
max-frequency = <96000000>;
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <8>;
max-frequency = <96000000>;
non-removable;
cap-sd-highspeed;
cap-mmc-highspeed;
@ -1204,18 +1204,18 @@ sdcc1: mmc@12400000 {
};
sdcc3: mmc@12180000 {
compatible = "arm,pl18x", "arm,primecell";
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
status = "disabled";
reg = <0x12180000 0x2000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
reg = <0x12180000 0x2000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <8>;
clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <192000000>;
max-frequency = <192000000>;
sd-uhs-sdr104;
sd-uhs-ddr50;
vqmmc-supply = <&vsdcc_fixed>;

6
arch/arm/boot/dts/qcom-mdm9615.dtsi
View File

@ -362,7 +362,7 @@ sdcc1: mmc@12180000 {
arm,primecell-periphid = <0x00051180>;
reg = <0x12180000 0x2000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
interrupt-names = "cmd_irq";
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <8>;
@ -382,7 +382,7 @@ sdcc2: mmc@12140000 {
status = "disabled";
reg = <0x12140000 0x2000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
interrupt-names = "cmd_irq";
clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <4>;
@ -412,7 +412,7 @@ rpm: rpm@108000 {
interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ack", "err", "wakeup";
interrupt-names = "ack", "err", "wakeup";
regulators {
compatible = "qcom,rpm-pm8018-regulators";

110
arch/arm/boot/dts/qcom-msm8660.dtsi
View File

@ -392,24 +392,24 @@ vibrator@4a {
};
l2cc: clock-controller@2082000 {
compatible = "qcom,kpss-gcc", "syscon";
reg = <0x02082000 0x1000>;
compatible = "qcom,kpss-gcc", "syscon";
reg = <0x02082000 0x1000>;
};
rpm: rpm@104000 {
compatible = "qcom,rpm-msm8660";
reg = <0x00104000 0x1000>;
qcom,ipc = <&l2cc 0x8 2>;
compatible = "qcom,rpm-msm8660";
reg = <0x00104000 0x1000>;
qcom,ipc = <&l2cc 0x8 2>;
interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ack", "err", "wakeup";
interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ack", "err", "wakeup";
clocks = <&gcc RPM_MSG_RAM_H_CLK>;
clock-names = "ram";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc";
compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc";
#clock-cells = <1>;
};
@ -486,80 +486,80 @@ amba {
#size-cells = <1>;
ranges;
sdcc1: mmc@12400000 {
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
reg = <0x12400000 0x8000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <8>;
max-frequency = <48000000>;
reg = <0x12400000 0x8000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <8>;
max-frequency = <48000000>;
non-removable;
cap-sd-highspeed;
cap-mmc-highspeed;
};
sdcc2: mmc@12140000 {
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
reg = <0x12140000 0x8000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <8>;
max-frequency = <48000000>;
reg = <0x12140000 0x8000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <8>;
max-frequency = <48000000>;
cap-sd-highspeed;
cap-mmc-highspeed;
};
sdcc3: mmc@12180000 {
compatible = "arm,pl18x", "arm,primecell";
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
status = "disabled";
reg = <0x12180000 0x8000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <4>;
status = "disabled";
reg = <0x12180000 0x8000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <4>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <48000000>;
max-frequency = <48000000>;
no-1-8-v;
};
sdcc4: mmc@121c0000 {
compatible = "arm,pl18x", "arm,primecell";
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
status = "disabled";
reg = <0x121c0000 0x8000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <4>;
max-frequency = <48000000>;
status = "disabled";
reg = <0x121c0000 0x8000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <4>;
max-frequency = <48000000>;
cap-sd-highspeed;
cap-mmc-highspeed;
};
sdcc5: mmc@12200000 {
compatible = "arm,pl18x", "arm,primecell";
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
status = "disabled";
reg = <0x12200000 0x8000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <4>;
status = "disabled";
reg = <0x12200000 0x8000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <4>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <48000000>;
max-frequency = <48000000>;
};
};

54
arch/arm/boot/dts/qcom-msm8960.dtsi
View File

@ -148,19 +148,19 @@ clock-controller@4000000 {
};
l2cc: clock-controller@2011000 {
compatible = "qcom,kpss-gcc", "syscon";
reg = <0x2011000 0x1000>;
compatible = "qcom,kpss-gcc", "syscon";
reg = <0x2011000 0x1000>;
};
rpm@108000 {
compatible = "qcom,rpm-msm8960";
reg = <0x108000 0x1000>;
qcom,ipc = <&l2cc 0x8 2>;
compatible = "qcom,rpm-msm8960";
reg = <0x108000 0x1000>;
qcom,ipc = <&l2cc 0x8 2>;
interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ack", "err", "wakeup";
interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ack", "err", "wakeup";
regulators {
compatible = "qcom,rpm-pm8921-regulators";
@ -268,16 +268,16 @@ amba {
#size-cells = <1>;
ranges;
sdcc1: mmc@12400000 {
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
reg = <0x12400000 0x8000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <8>;
max-frequency = <96000000>;
reg = <0x12400000 0x8000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <8>;
max-frequency = <96000000>;
non-removable;
cap-sd-highspeed;
cap-mmc-highspeed;
@ -285,18 +285,18 @@ sdcc1: mmc@12400000 {
};
sdcc3: mmc@12180000 {
compatible = "arm,pl18x", "arm,primecell";
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
status = "disabled";
reg = <0x12180000 0x8000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <4>;
status = "disabled";
reg = <0x12180000 0x8000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
clock-names = "mclk", "apb_pclk";
bus-width = <4>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <192000000>;
max-frequency = <192000000>;
no-1-8-v;
vmmc-supply = <&vsdcc_fixed>;
};

6
arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts
View File

@ -78,9 +78,9 @@ &blsp1_uart2 {
&imem {
reboot-mode {
mode-normal = <0x77665501>;
mode-bootloader = <0x77665500>;
mode-recovery = <0x77665502>;
mode-normal = <0x77665501>;
mode-bootloader = <0x77665500>;
mode-recovery = <0x77665502>;
};
};