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Merge branch 'phy-mediatek-reorg'

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Sky Huang says:

====================
Re-organize MediaTek ethernet phy drivers and propose mtk-phy-lib

This patchset comes from patch 1/9, 3/9, 4/9, 5/9 and 7/9 of:
https://lore.kernel.org/netdev/20241004102413.5838-1-SkyLake.Huang@mediatek.com/

This patchset changes MediaTek's ethernet phy's folder structure and
integrates helper functions, including LED & token ring manipulation,
into mtk-phy-lib.

---
Change in v2:
- Add correct Reviewed-by tag in each patch.

Change in v3:
[patch 4/5]
- Fix kernel test robot error by adding missing MTK_NET_PHYLIB.
====================

Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
This commit is contained in:
David S. Miller 2024-11-13 13:06:04 +00:00
commit 31a1f8752f
9 changed files with 438 additions and 307 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
MAINTAINERS
View File

@ -14439,8 +14439,10 @@ M: Qingfang Deng <dqfext@gmail.com>
M: SkyLake Huang <SkyLake.Huang@mediatek.com>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/phy/mediatek-ge-soc.c
F: drivers/net/phy/mediatek-ge.c
F: drivers/net/phy/mediatek/mtk-ge-soc.c
F: drivers/net/phy/mediatek/mtk-phy-lib.c
F: drivers/net/phy/mediatek/mtk-ge.c
F: drivers/net/phy/mediatek/mtk.h
F: drivers/phy/mediatek/phy-mtk-xfi-tphy.c
MEDIATEK I2C CONTROLLER DRIVER

17
drivers/net/phy/Kconfig
View File

@ -266,22 +266,7 @@ config MAXLINEAR_GPHY
Support for the Maxlinear GPY115, GPY211, GPY212, GPY215,
GPY241, GPY245 PHYs.
config MEDIATEK_GE_PHY
tristate "MediaTek Gigabit Ethernet PHYs"
help
Supports the MediaTek Gigabit Ethernet PHYs.
config MEDIATEK_GE_SOC_PHY
tristate "MediaTek SoC Ethernet PHYs"
depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
depends on NVMEM_MTK_EFUSE
help
Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
Include support for built-in Ethernet PHYs which are present in
the MT7981 and MT7988 SoCs. These PHYs need calibration data
present in the SoCs efuse and will dynamically calibrate VCM
(common-mode voltage) during startup.
source "drivers/net/phy/mediatek/Kconfig"
config MICREL_PHY
tristate "Micrel PHYs"

3
drivers/net/phy/Makefile
View File

@ -74,8 +74,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o
obj-$(CONFIG_MARVELL_88Q2XXX_PHY) += marvell-88q2xxx.o
obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o
obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o
obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o
obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o
obj-y += mediatek/
obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
obj-$(CONFIG_MICREL_PHY) += micrel.o

27
drivers/net/phy/mediatek/Kconfig Normal file
View File

@ -0,0 +1,27 @@
# SPDX-License-Identifier: GPL-2.0-only
config MTK_NET_PHYLIB
tristate
config MEDIATEK_GE_PHY
tristate "MediaTek Gigabit Ethernet PHYs"
select MTK_NET_PHYLIB
help
Supports the MediaTek non-built-in Gigabit Ethernet PHYs.
Non-built-in Gigabit Ethernet PHYs include mt7530/mt7531.
You may find mt7530 inside mt7621. This driver shares some
common operations with MediaTek SoC built-in Gigabit
Ethernet PHYs.
config MEDIATEK_GE_SOC_PHY
tristate "MediaTek SoC Ethernet PHYs"
depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
depends on NVMEM_MTK_EFUSE
select MTK_NET_PHYLIB
help
Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
Include support for built-in Ethernet PHYs which are present in
the MT7981 and MT7988 SoCs. These PHYs need calibration data
present in the SoCs efuse and will dynamically calibrate VCM
(common-mode voltage) during startup.

4
drivers/net/phy/mediatek/Makefile Normal file
View File

@ -0,0 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_MTK_NET_PHYLIB) += mtk-phy-lib.o
obj-$(CONFIG_MEDIATEK_GE_PHY) += mtk-ge.o
obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mtk-ge-soc.o

298
drivers/net/phy/mediatek-ge-soc.c → drivers/net/phy/mediatek/mtk-ge-soc.c
View File

@ -8,6 +8,8 @@
#include <linux/phy.h>
#include <linux/regmap.h>
#include "mtk.h"
#define MTK_GPHY_ID_MT7981 0x03a29461
#define MTK_GPHY_ID_MT7988 0x03a29481
@ -210,41 +212,6 @@
#define MTK_PHY_DA_TX_R50_PAIR_D 0x540
/* Registers on MDIO_MMD_VEND2 */
#define MTK_PHY_LED0_ON_CTRL 0x24
#define MTK_PHY_LED1_ON_CTRL 0x26
#define MTK_PHY_LED_ON_MASK GENMASK(6, 0)
#define MTK_PHY_LED_ON_LINK1000 BIT(0)
#define MTK_PHY_LED_ON_LINK100 BIT(1)
#define MTK_PHY_LED_ON_LINK10 BIT(2)
#define MTK_PHY_LED_ON_LINK (MTK_PHY_LED_ON_LINK10 |\
MTK_PHY_LED_ON_LINK100 |\
MTK_PHY_LED_ON_LINK1000)
#define MTK_PHY_LED_ON_LINKDOWN BIT(3)
#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */
#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */
#define MTK_PHY_LED_ON_FORCE_ON BIT(6)
#define MTK_PHY_LED_ON_POLARITY BIT(14)
#define MTK_PHY_LED_ON_ENABLE BIT(15)
#define MTK_PHY_LED0_BLINK_CTRL 0x25
#define MTK_PHY_LED1_BLINK_CTRL 0x27
#define MTK_PHY_LED_BLINK_1000TX BIT(0)
#define MTK_PHY_LED_BLINK_1000RX BIT(1)
#define MTK_PHY_LED_BLINK_100TX BIT(2)
#define MTK_PHY_LED_BLINK_100RX BIT(3)
#define MTK_PHY_LED_BLINK_10TX BIT(4)
#define MTK_PHY_LED_BLINK_10RX BIT(5)
#define MTK_PHY_LED_BLINK_RX (MTK_PHY_LED_BLINK_10RX |\
MTK_PHY_LED_BLINK_100RX |\
MTK_PHY_LED_BLINK_1000RX)
#define MTK_PHY_LED_BLINK_TX (MTK_PHY_LED_BLINK_10TX |\
MTK_PHY_LED_BLINK_100TX |\
MTK_PHY_LED_BLINK_1000TX)
#define MTK_PHY_LED_BLINK_COLLISION BIT(6)
#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7)
#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8)
#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9)
#define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1)
#define MTK_PHY_RG_BG_RASEL 0x115
@ -299,29 +266,11 @@ enum CAL_MODE {
SW_M
};
#define MTK_PHY_LED_STATE_FORCE_ON 0
#define MTK_PHY_LED_STATE_FORCE_BLINK 1
#define MTK_PHY_LED_STATE_NETDEV 2
struct mtk_socphy_priv {
unsigned long led_state;
};
struct mtk_socphy_shared {
u32 boottrap;
struct mtk_socphy_priv priv[4];
};
static int mtk_socphy_read_page(struct phy_device *phydev)
{
return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
}
static int mtk_socphy_write_page(struct phy_device *phydev, int page)
{
return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
}
/* One calibration cycle consists of:
* 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
* until AD_CAL_COMP is ready to output calibration result.
@ -1172,76 +1121,23 @@ static int mt798x_phy_config_init(struct phy_device *phydev)
return mt798x_phy_calibration(phydev);
}
static int mt798x_phy_hw_led_on_set(struct phy_device *phydev, u8 index,
bool on)
{
unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
struct mtk_socphy_priv *priv = phydev->priv;
bool changed;
if (on)
changed = !test_and_set_bit(bit_on, &priv->led_state);
else
changed = !!test_and_clear_bit(bit_on, &priv->led_state);
changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV +
(index ? 16 : 0), &priv->led_state);
if (changed)
return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
MTK_PHY_LED1_ON_CTRL :
MTK_PHY_LED0_ON_CTRL,
MTK_PHY_LED_ON_MASK,
on ? MTK_PHY_LED_ON_FORCE_ON : 0);
else
return 0;
}
static int mt798x_phy_hw_led_blink_set(struct phy_device *phydev, u8 index,
bool blinking)
{
unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
(index ? 16 : 0);
struct mtk_socphy_priv *priv = phydev->priv;
bool changed;
if (blinking)
changed = !test_and_set_bit(bit_blink, &priv->led_state);
else
changed = !!test_and_clear_bit(bit_blink, &priv->led_state);
changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV +
(index ? 16 : 0), &priv->led_state);
if (changed)
return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
MTK_PHY_LED1_BLINK_CTRL :
MTK_PHY_LED0_BLINK_CTRL,
blinking ?
MTK_PHY_LED_BLINK_FORCE_BLINK : 0);
else
return 0;
}
static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index,
unsigned long *delay_on,
unsigned long *delay_off)
{
bool blinking = false;
int err = 0;
int err;
if (index > 1)
return -EINVAL;
err = mtk_phy_led_num_dly_cfg(index, delay_on, delay_off, &blinking);
if (err < 0)
return err;
if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
blinking = true;
*delay_on = 50;
*delay_off = 50;
}
err = mt798x_phy_hw_led_blink_set(phydev, index, blinking);
err = mtk_phy_hw_led_blink_set(phydev, index, blinking);
if (err)
return err;
return mt798x_phy_hw_led_on_set(phydev, index, false);
return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK,
false);
}
static int mt798x_phy_led_brightness_set(struct phy_device *phydev,
@ -1249,11 +1145,12 @@ static int mt798x_phy_led_brightness_set(struct phy_device *phydev,
{
int err;
err = mt798x_phy_hw_led_blink_set(phydev, index, false);
err = mtk_phy_hw_led_blink_set(phydev, index, false);
if (err)
return err;
return mt798x_phy_hw_led_on_set(phydev, index, (value != LED_OFF));
return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK,
(value != LED_OFF));
}
static const unsigned long supported_triggers =
@ -1269,155 +1166,26 @@ static const unsigned long supported_triggers =
static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
unsigned long rules)
{
if (index > 1)
return -EINVAL;
/* All combinations of the supported triggers are allowed */
if (rules & ~supported_triggers)
return -EOPNOTSUPP;
return 0;
};
return mtk_phy_led_hw_is_supported(phydev, index, rules,
supported_triggers);
}
static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
unsigned long *rules)
{
unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
(index ? 16 : 0);
unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
struct mtk_socphy_priv *priv = phydev->priv;
int on, blink;
if (index > 1)
return -EINVAL;
on = phy_read_mmd(phydev, MDIO_MMD_VEND2,
index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL);
if (on < 0)
return -EIO;
blink = phy_read_mmd(phydev, MDIO_MMD_VEND2,
index ? MTK_PHY_LED1_BLINK_CTRL :
MTK_PHY_LED0_BLINK_CTRL);
if (blink < 0)
return -EIO;
if ((on & (MTK_PHY_LED_ON_LINK | MTK_PHY_LED_ON_FDX |
MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) ||
(blink & (MTK_PHY_LED_BLINK_RX | MTK_PHY_LED_BLINK_TX)))
set_bit(bit_netdev, &priv->led_state);
else
clear_bit(bit_netdev, &priv->led_state);
if (on & MTK_PHY_LED_ON_FORCE_ON)
set_bit(bit_on, &priv->led_state);
else
clear_bit(bit_on, &priv->led_state);
if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK)
set_bit(bit_blink, &priv->led_state);
else
clear_bit(bit_blink, &priv->led_state);
if (!rules)
return 0;
if (on & MTK_PHY_LED_ON_LINK)
*rules |= BIT(TRIGGER_NETDEV_LINK);
if (on & MTK_PHY_LED_ON_LINK10)
*rules |= BIT(TRIGGER_NETDEV_LINK_10);
if (on & MTK_PHY_LED_ON_LINK100)
*rules |= BIT(TRIGGER_NETDEV_LINK_100);
if (on & MTK_PHY_LED_ON_LINK1000)
*rules |= BIT(TRIGGER_NETDEV_LINK_1000);
if (on & MTK_PHY_LED_ON_FDX)
*rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX);
if (on & MTK_PHY_LED_ON_HDX)
*rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX);
if (blink & MTK_PHY_LED_BLINK_RX)
*rules |= BIT(TRIGGER_NETDEV_RX);
if (blink & MTK_PHY_LED_BLINK_TX)
*rules |= BIT(TRIGGER_NETDEV_TX);
return 0;
return mtk_phy_led_hw_ctrl_get(phydev, index, rules,
MTK_GPHY_LED_ON_SET,
MTK_GPHY_LED_RX_BLINK_SET,
MTK_GPHY_LED_TX_BLINK_SET);
};
static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
unsigned long rules)
{
unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
struct mtk_socphy_priv *priv = phydev->priv;
u16 on = 0, blink = 0;
int ret;
if (index > 1)
return -EINVAL;
if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
on |= MTK_PHY_LED_ON_FDX;
if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
on |= MTK_PHY_LED_ON_HDX;
if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))
on |= MTK_PHY_LED_ON_LINK10;
if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
on |= MTK_PHY_LED_ON_LINK100;
if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
on |= MTK_PHY_LED_ON_LINK1000;
if (rules & BIT(TRIGGER_NETDEV_RX)) {
blink |= (on & MTK_PHY_LED_ON_LINK) ?
(((on & MTK_PHY_LED_ON_LINK10) ?
MTK_PHY_LED_BLINK_10RX : 0) |
((on & MTK_PHY_LED_ON_LINK100) ?
MTK_PHY_LED_BLINK_100RX : 0) |
((on & MTK_PHY_LED_ON_LINK1000) ?
MTK_PHY_LED_BLINK_1000RX : 0)) :
MTK_PHY_LED_BLINK_RX;
}
if (rules & BIT(TRIGGER_NETDEV_TX)) {
blink |= (on & MTK_PHY_LED_ON_LINK) ?
(((on & MTK_PHY_LED_ON_LINK10) ?
MTK_PHY_LED_BLINK_10TX : 0) |
((on & MTK_PHY_LED_ON_LINK100) ?
MTK_PHY_LED_BLINK_100TX : 0) |
((on & MTK_PHY_LED_ON_LINK1000) ?
MTK_PHY_LED_BLINK_1000TX : 0)) :
MTK_PHY_LED_BLINK_TX;
}
if (blink || on)
set_bit(bit_netdev, &priv->led_state);
else
clear_bit(bit_netdev, &priv->led_state);
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
MTK_PHY_LED1_ON_CTRL :
MTK_PHY_LED0_ON_CTRL,
MTK_PHY_LED_ON_FDX |
MTK_PHY_LED_ON_HDX |
MTK_PHY_LED_ON_LINK,
on);
if (ret)
return ret;
return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
MTK_PHY_LED1_BLINK_CTRL :
MTK_PHY_LED0_BLINK_CTRL, blink);
return mtk_phy_led_hw_ctrl_set(phydev, index, rules,
MTK_GPHY_LED_ON_SET,
MTK_GPHY_LED_RX_BLINK_SET,
MTK_GPHY_LED_TX_BLINK_SET);
};
static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num)
@ -1492,14 +1260,6 @@ static int mt7988_phy_probe_shared(struct phy_device *phydev)
return 0;
}
static void mt798x_phy_leds_state_init(struct phy_device *phydev)
{
int i;
for (i = 0; i < 2; ++i)
mt798x_phy_led_hw_control_get(phydev, i, NULL);
}
static int mt7988_phy_probe(struct phy_device *phydev)
{
struct mtk_socphy_shared *shared;
@ -1525,7 +1285,7 @@ static int mt7988_phy_probe(struct phy_device *phydev)
phydev->priv = priv;
mt798x_phy_leds_state_init(phydev);
mtk_phy_leds_state_init(phydev);
err = mt7988_phy_fix_leds_polarities(phydev);
if (err)
@ -1552,7 +1312,7 @@ static int mt7981_phy_probe(struct phy_device *phydev)
phydev->priv = priv;
mt798x_phy_leds_state_init(phydev);
mtk_phy_leds_state_init(phydev);
return mt798x_phy_calibration(phydev);
}
@ -1567,8 +1327,8 @@ static struct phy_driver mtk_socphy_driver[] = {
.probe = mt7981_phy_probe,
.suspend = genphy_suspend,
.resume = genphy_resume,
.read_page = mtk_socphy_read_page,
.write_page = mtk_socphy_write_page,
.read_page = mtk_phy_read_page,
.write_page = mtk_phy_write_page,
.led_blink_set = mt798x_phy_led_blink_set,
.led_brightness_set = mt798x_phy_led_brightness_set,
.led_hw_is_supported = mt798x_phy_led_hw_is_supported,
@ -1584,8 +1344,8 @@ static struct phy_driver mtk_socphy_driver[] = {
.probe = mt7988_phy_probe,
.suspend = genphy_suspend,
.resume = genphy_resume,
.read_page = mtk_socphy_read_page,
.write_page = mtk_socphy_write_page,
.read_page = mtk_phy_read_page,
.write_page = mtk_phy_write_page,
.led_blink_set = mt798x_phy_led_blink_set,
.led_brightness_set = mt798x_phy_led_brightness_set,
.led_hw_is_supported = mt798x_phy_led_hw_is_supported,

31
drivers/net/phy/mediatek-ge.c → drivers/net/phy/mediatek/mtk-ge.c
View File

@ -3,6 +3,11 @@
#include <linux/module.h>
#include <linux/phy.h>
#include "mtk.h"
#define MTK_GPHY_ID_MT7530 0x03a29412
#define MTK_GPHY_ID_MT7531 0x03a29441
#define MTK_EXT_PAGE_ACCESS 0x1f
#define MTK_PHY_PAGE_STANDARD 0x0000
#define MTK_PHY_PAGE_EXTENDED 0x0001
@ -11,16 +16,6 @@
#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
static int mtk_gephy_read_page(struct phy_device *phydev)
{
return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
}
static int mtk_gephy_write_page(struct phy_device *phydev, int page)
{
return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
}
static void mtk_gephy_config_init(struct phy_device *phydev)
{
/* Enable HW auto downshift */
@ -67,7 +62,7 @@ static int mt7531_phy_config_init(struct phy_device *phydev)
static struct phy_driver mtk_gephy_driver[] = {
{
PHY_ID_MATCH_EXACT(0x03a29412),
PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7530),
.name = "MediaTek MT7530 PHY",
.config_init = mt7530_phy_config_init,
/* Interrupts are handled by the switch, not the PHY
@ -77,11 +72,11 @@ static struct phy_driver mtk_gephy_driver[] = {
.handle_interrupt = genphy_handle_interrupt_no_ack,
.suspend = genphy_suspend,
.resume = genphy_resume,
.read_page = mtk_gephy_read_page,
.write_page = mtk_gephy_write_page,
.read_page = mtk_phy_read_page,
.write_page = mtk_phy_write_page,
},
{
PHY_ID_MATCH_EXACT(0x03a29441),
PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7531),
.name = "MediaTek MT7531 PHY",
.config_init = mt7531_phy_config_init,
/* Interrupts are handled by the switch, not the PHY
@ -91,16 +86,16 @@ static struct phy_driver mtk_gephy_driver[] = {
.handle_interrupt = genphy_handle_interrupt_no_ack,
.suspend = genphy_suspend,
.resume = genphy_resume,
.read_page = mtk_gephy_read_page,
.write_page = mtk_gephy_write_page,
.read_page = mtk_phy_read_page,
.write_page = mtk_phy_write_page,
},
};
module_phy_driver(mtk_gephy_driver);
static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
{ PHY_ID_MATCH_EXACT(0x03a29441) },
{ PHY_ID_MATCH_EXACT(0x03a29412) },
{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7530) },
{ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7531) },
{ }
};

270
drivers/net/phy/mediatek/mtk-phy-lib.c Normal file
View File

@ -0,0 +1,270 @@
// SPDX-License-Identifier: GPL-2.0
#include <linux/phy.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include "mtk.h"
int mtk_phy_read_page(struct phy_device *phydev)
{
return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
}
EXPORT_SYMBOL_GPL(mtk_phy_read_page);
int mtk_phy_write_page(struct phy_device *phydev, int page)
{
return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
}
EXPORT_SYMBOL_GPL(mtk_phy_write_page);
int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
unsigned long rules,
unsigned long supported_triggers)
{
if (index > 1)
return -EINVAL;
/* All combinations of the supported triggers are allowed */
if (rules & ~supported_triggers)
return -EOPNOTSUPP;
return 0;
}
EXPORT_SYMBOL_GPL(mtk_phy_led_hw_is_supported);
int mtk_phy_led_hw_ctrl_get(struct phy_device *phydev, u8 index,
unsigned long *rules, u16 on_set,
u16 rx_blink_set, u16 tx_blink_set)
{
unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
(index ? 16 : 0);
unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
struct mtk_socphy_priv *priv = phydev->priv;
int on, blink;
if (index > 1)
return -EINVAL;
on = phy_read_mmd(phydev, MDIO_MMD_VEND2,
index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL);
if (on < 0)
return -EIO;
blink = phy_read_mmd(phydev, MDIO_MMD_VEND2,
index ? MTK_PHY_LED1_BLINK_CTRL :
MTK_PHY_LED0_BLINK_CTRL);
if (blink < 0)
return -EIO;
if ((on & (on_set | MTK_PHY_LED_ON_FDX |
MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) ||
(blink & (rx_blink_set | tx_blink_set)))
set_bit(bit_netdev, &priv->led_state);
else
clear_bit(bit_netdev, &priv->led_state);
if (on & MTK_PHY_LED_ON_FORCE_ON)
set_bit(bit_on, &priv->led_state);
else
clear_bit(bit_on, &priv->led_state);
if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK)
set_bit(bit_blink, &priv->led_state);
else
clear_bit(bit_blink, &priv->led_state);
if (!rules)
return 0;
if (on & on_set)
*rules |= BIT(TRIGGER_NETDEV_LINK);
if (on & MTK_PHY_LED_ON_LINK10)
*rules |= BIT(TRIGGER_NETDEV_LINK_10);
if (on & MTK_PHY_LED_ON_LINK100)
*rules |= BIT(TRIGGER_NETDEV_LINK_100);
if (on & MTK_PHY_LED_ON_LINK1000)
*rules |= BIT(TRIGGER_NETDEV_LINK_1000);
if (on & MTK_PHY_LED_ON_LINK2500)
*rules |= BIT(TRIGGER_NETDEV_LINK_2500);
if (on & MTK_PHY_LED_ON_FDX)
*rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX);
if (on & MTK_PHY_LED_ON_HDX)
*rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX);
if (blink & rx_blink_set)
*rules |= BIT(TRIGGER_NETDEV_RX);
if (blink & tx_blink_set)
*rules |= BIT(TRIGGER_NETDEV_TX);
return 0;
}
EXPORT_SYMBOL_GPL(mtk_phy_led_hw_ctrl_get);
int mtk_phy_led_hw_ctrl_set(struct phy_device *phydev, u8 index,
unsigned long rules, u16 on_set,
u16 rx_blink_set, u16 tx_blink_set)
{
unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
struct mtk_socphy_priv *priv = phydev->priv;
u16 on = 0, blink = 0;
int ret;
if (index > 1)
return -EINVAL;
if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
on |= MTK_PHY_LED_ON_FDX;
if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
on |= MTK_PHY_LED_ON_HDX;
if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))
on |= MTK_PHY_LED_ON_LINK10;
if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
on |= MTK_PHY_LED_ON_LINK100;
if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
on |= MTK_PHY_LED_ON_LINK1000;
if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK)))
on |= MTK_PHY_LED_ON_LINK2500;
if (rules & BIT(TRIGGER_NETDEV_RX)) {
if (on & on_set) {
if (on & MTK_PHY_LED_ON_LINK10)
blink |= MTK_PHY_LED_BLINK_10RX;
if (on & MTK_PHY_LED_ON_LINK100)
blink |= MTK_PHY_LED_BLINK_100RX;
if (on & MTK_PHY_LED_ON_LINK1000)
blink |= MTK_PHY_LED_BLINK_1000RX;
if (on & MTK_PHY_LED_ON_LINK2500)
blink |= MTK_PHY_LED_BLINK_2500RX;
} else {
blink |= rx_blink_set;
}
}
if (rules & BIT(TRIGGER_NETDEV_TX)) {
if (on & on_set) {
if (on & MTK_PHY_LED_ON_LINK10)
blink |= MTK_PHY_LED_BLINK_10TX;
if (on & MTK_PHY_LED_ON_LINK100)
blink |= MTK_PHY_LED_BLINK_100TX;
if (on & MTK_PHY_LED_ON_LINK1000)
blink |= MTK_PHY_LED_BLINK_1000TX;
if (on & MTK_PHY_LED_ON_LINK2500)
blink |= MTK_PHY_LED_BLINK_2500TX;
} else {
blink |= tx_blink_set;
}
}
if (blink || on)
set_bit(bit_netdev, &priv->led_state);
else
clear_bit(bit_netdev, &priv->led_state);
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX | on_set,
on);
if (ret)
return ret;
return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
MTK_PHY_LED1_BLINK_CTRL :
MTK_PHY_LED0_BLINK_CTRL, blink);
}
EXPORT_SYMBOL_GPL(mtk_phy_led_hw_ctrl_set);
int mtk_phy_led_num_dly_cfg(u8 index, unsigned long *delay_on,
unsigned long *delay_off, bool *blinking)
{
if (index > 1)
return -EINVAL;
if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
*blinking = true;
*delay_on = 50;
*delay_off = 50;
}
return 0;
}
EXPORT_SYMBOL_GPL(mtk_phy_led_num_dly_cfg);
int mtk_phy_hw_led_on_set(struct phy_device *phydev, u8 index,
u16 led_on_mask, bool on)
{
unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
struct mtk_socphy_priv *priv = phydev->priv;
bool changed;
if (on)
changed = !test_and_set_bit(bit_on, &priv->led_state);
else
changed = !!test_and_clear_bit(bit_on, &priv->led_state);
changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV +
(index ? 16 : 0), &priv->led_state);
if (changed)
return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
MTK_PHY_LED1_ON_CTRL :
MTK_PHY_LED0_ON_CTRL,
led_on_mask,
on ? MTK_PHY_LED_ON_FORCE_ON : 0);
else
return 0;
}
EXPORT_SYMBOL_GPL(mtk_phy_hw_led_on_set);
int mtk_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, bool blinking)
{
unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
(index ? 16 : 0);
struct mtk_socphy_priv *priv = phydev->priv;
bool changed;
if (blinking)
changed = !test_and_set_bit(bit_blink, &priv->led_state);
else
changed = !!test_and_clear_bit(bit_blink, &priv->led_state);
changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV +
(index ? 16 : 0), &priv->led_state);
if (changed)
return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
MTK_PHY_LED1_BLINK_CTRL :
MTK_PHY_LED0_BLINK_CTRL,
blinking ?
MTK_PHY_LED_BLINK_FORCE_BLINK : 0);
else
return 0;
}
EXPORT_SYMBOL_GPL(mtk_phy_hw_led_blink_set);
void mtk_phy_leds_state_init(struct phy_device *phydev)
{
int i;
for (i = 0; i < 2; ++i)
phydev->drv->led_hw_control_get(phydev, i, NULL);
}
EXPORT_SYMBOL_GPL(mtk_phy_leds_state_init);
MODULE_DESCRIPTION("MediaTek Ethernet PHY driver common");
MODULE_AUTHOR("Sky Huang <SkyLake.Huang@mediatek.com>");
MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
MODULE_LICENSE("GPL");

89
drivers/net/phy/mediatek/mtk.h Normal file
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/* SPDX-License-Identifier: GPL-2.0
*
* Common definition for Mediatek Ethernet PHYs
* Author: SkyLake Huang <SkyLake.Huang@mediatek.com>
* Copyright (c) 2024 MediaTek Inc.
*/
#ifndef _MTK_EPHY_H_
#define _MTK_EPHY_H_
#define MTK_EXT_PAGE_ACCESS 0x1f
/* Registers on MDIO_MMD_VEND2 */
#define MTK_PHY_LED0_ON_CTRL 0x24
#define MTK_PHY_LED1_ON_CTRL 0x26
#define MTK_GPHY_LED_ON_MASK GENMASK(6, 0)
#define MTK_2P5GPHY_LED_ON_MASK GENMASK(7, 0)
#define MTK_PHY_LED_ON_LINK1000 BIT(0)
#define MTK_PHY_LED_ON_LINK100 BIT(1)
#define MTK_PHY_LED_ON_LINK10 BIT(2)
#define MTK_PHY_LED_ON_LINKDOWN BIT(3)
#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */
#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */
#define MTK_PHY_LED_ON_FORCE_ON BIT(6)
#define MTK_PHY_LED_ON_LINK2500 BIT(7)
#define MTK_PHY_LED_ON_POLARITY BIT(14)
#define MTK_PHY_LED_ON_ENABLE BIT(15)
#define MTK_PHY_LED0_BLINK_CTRL 0x25
#define MTK_PHY_LED1_BLINK_CTRL 0x27
#define MTK_PHY_LED_BLINK_1000TX BIT(0)
#define MTK_PHY_LED_BLINK_1000RX BIT(1)
#define MTK_PHY_LED_BLINK_100TX BIT(2)
#define MTK_PHY_LED_BLINK_100RX BIT(3)
#define MTK_PHY_LED_BLINK_10TX BIT(4)
#define MTK_PHY_LED_BLINK_10RX BIT(5)
#define MTK_PHY_LED_BLINK_COLLISION BIT(6)
#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7)
#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8)
#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9)
#define MTK_PHY_LED_BLINK_2500TX BIT(10)
#define MTK_PHY_LED_BLINK_2500RX BIT(11)
#define MTK_GPHY_LED_ON_SET (MTK_PHY_LED_ON_LINK1000 | \
MTK_PHY_LED_ON_LINK100 | \
MTK_PHY_LED_ON_LINK10)
#define MTK_GPHY_LED_RX_BLINK_SET (MTK_PHY_LED_BLINK_1000RX | \
MTK_PHY_LED_BLINK_100RX | \
MTK_PHY_LED_BLINK_10RX)
#define MTK_GPHY_LED_TX_BLINK_SET (MTK_PHY_LED_BLINK_1000RX | \
MTK_PHY_LED_BLINK_100RX | \
MTK_PHY_LED_BLINK_10RX)
#define MTK_2P5GPHY_LED_ON_SET (MTK_PHY_LED_ON_LINK2500 | \
MTK_GPHY_LED_ON_SET)
#define MTK_2P5GPHY_LED_RX_BLINK_SET (MTK_PHY_LED_BLINK_2500RX | \
MTK_GPHY_LED_RX_BLINK_SET)
#define MTK_2P5GPHY_LED_TX_BLINK_SET (MTK_PHY_LED_BLINK_2500RX | \
MTK_GPHY_LED_TX_BLINK_SET)
#define MTK_PHY_LED_STATE_FORCE_ON 0
#define MTK_PHY_LED_STATE_FORCE_BLINK 1
#define MTK_PHY_LED_STATE_NETDEV 2
struct mtk_socphy_priv {
unsigned long led_state;
};
int mtk_phy_read_page(struct phy_device *phydev);
int mtk_phy_write_page(struct phy_device *phydev, int page);
int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
unsigned long rules,
unsigned long supported_triggers);
int mtk_phy_led_hw_ctrl_set(struct phy_device *phydev, u8 index,
unsigned long rules, u16 on_set,
u16 rx_blink_set, u16 tx_blink_set);
int mtk_phy_led_hw_ctrl_get(struct phy_device *phydev, u8 index,
unsigned long *rules, u16 on_set,
u16 rx_blink_set, u16 tx_blink_set);
int mtk_phy_led_num_dly_cfg(u8 index, unsigned long *delay_on,
unsigned long *delay_off, bool *blinking);
int mtk_phy_hw_led_on_set(struct phy_device *phydev, u8 index,
u16 led_on_mask, bool on);
int mtk_phy_hw_led_blink_set(struct phy_device *phydev, u8 index,
bool blinking);
void mtk_phy_leds_state_init(struct phy_device *phydev);
#endif /* _MTK_EPHY_H_ */