github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-12 16:18:45 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity

riscv: smp: Clarify comment "cache" -> "instruction cache"

Browse Source 
local_flush_icache_all() only flushes and synchronizes the *instruction*
cache, not the data cache. Since RISC-V does have a cbo.flush
instruction for data cache flush, clarify the comment to avoid
confusion.

Fixes: 58661a30f1 ("riscv: Flush the instruction cache during SMP bringup")
Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
Link: https://patch.msgid.link/20260204-riscv-smp-comment-update-2026-01-v1-2-8b77aa181530@iscas.ac.cn
Signed-off-by: Paul Walmsley <pjw@kernel.org>
This commit is contained in:
Vivian Wang 2026-04-04 18:42:40 -06:00 committed by Paul Walmsley
parent fe0cf82fde
commit 31454cb5f1
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/riscv/kernel/smpboot.c
View File

@ -251,8 +251,8 @@ asmlinkage __visible void smp_callin(void)
set_cpu_online(curr_cpuid, true);
/*
* Remote cache and TLB flushes are ignored while the CPU is offline,
* so flush them both right now just in case.
* Remote instruction cache and TLB flushes are ignored while the CPU
* is offline, so flush them both right now just in case.
*/
local_flush_icache_all();
local_flush_tlb_all();