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https://github.com/torvalds/linux.git
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Merge branch 'net-stmmac-multi-interface-stmmac'
Russell King says: ==================== net: stmmac: multi-interface stmmac This series adds a callback for platform glue to configure the stmmac core interface mode depending on the PHY interface mode that is being used. This is currently only called just before the dwmac core is reset since these signals are latched on reset. Included in this series are changes to s32 to move its PHY_INTF_SEL_x definitions out of the way of the dwmac core's signals which has more entitlement to use this name. We convert dwmac-imx as an example. Including other platform glue would make this series excessively large, but once this core code is merged, the individual platform glue updates can be posted one after another as they will be independent of each other. It is hoped that this callback can be used in future to reconfigure the dwmac core when the interface mode changes to support PHYs that change their interface mode, but we're nowhere near being able to do that yet. ==================== Link: https://patch.msgid.link/aQiWzyrXU_2hGJ4j@shell.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
commit
31113a452a
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@ -313,6 +313,16 @@ struct stmmac_safety_stats {
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#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
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#define DEFAULT_DMA_PBL 8
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/* phy_intf_sel_i and ACTPHYIF encodings */
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#define PHY_INTF_SEL_GMII_MII 0
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#define PHY_INTF_SEL_RGMII 1
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#define PHY_INTF_SEL_SGMII 2
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#define PHY_INTF_SEL_TBI 3
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#define PHY_INTF_SEL_RMII 4
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#define PHY_INTF_SEL_RTBI 5
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#define PHY_INTF_SEL_SMII 6
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#define PHY_INTF_SEL_REVMII 7
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/* MSI defines */
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#define STMMAC_MSI_VEC_MAX 32
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@ -23,18 +23,13 @@
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#include "stmmac_platform.h"
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#define GPR_ENET_QOS_INTF_MODE_MASK GENMASK(21, 16)
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#define GPR_ENET_QOS_INTF_SEL_MII (0x0 << 16)
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#define GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 16)
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#define GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 16)
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#define GPR_ENET_QOS_INTF_SEL_MASK GENMASK(20, 16)
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#define GPR_ENET_QOS_CLK_GEN_EN (0x1 << 19)
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#define GPR_ENET_QOS_CLK_TX_CLK_SEL (0x1 << 20)
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#define GPR_ENET_QOS_RGMII_EN (0x1 << 21)
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#define MX93_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 0)
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#define MX93_GPR_ENET_QOS_INTF_MASK GENMASK(3, 1)
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#define MX93_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1)
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#define MX93_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1)
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#define MX93_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1)
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#define MX93_GPR_ENET_QOS_INTF_SEL_MASK GENMASK(3, 1)
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#define MX93_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0)
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#define MX93_GPR_ENET_QOS_CLK_SEL_MASK BIT_MASK(0)
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#define MX93_GPR_CLK_SEL_OFFSET (4)
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@ -44,13 +39,15 @@
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#define RMII_RESET_SPEED (0x3 << 14)
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#define CTRL_SPEED_MASK GENMASK(15, 14)
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struct imx_priv_data;
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struct imx_dwmac_ops {
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u32 addr_width;
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u32 flags;
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bool mac_rgmii_txclk_auto_adj;
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int (*fix_soc_reset)(struct stmmac_priv *priv, void __iomem *ioaddr);
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int (*set_intf_mode)(struct plat_stmmacenet_data *plat_dat);
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int (*set_intf_mode)(struct imx_priv_data *dwmac, u8 phy_intf_sel);
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void (*fix_mac_speed)(void *priv, int speed, unsigned int mode);
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};
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@ -67,79 +64,46 @@ struct imx_priv_data {
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struct plat_stmmacenet_data *plat_dat;
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};
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static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat)
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static int imx8mp_set_intf_mode(struct imx_priv_data *dwmac, u8 phy_intf_sel)
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{
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struct imx_priv_data *dwmac = plat_dat->bsp_priv;
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int val;
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unsigned int val;
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switch (plat_dat->phy_interface) {
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case PHY_INTERFACE_MODE_MII:
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val = GPR_ENET_QOS_INTF_SEL_MII;
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break;
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case PHY_INTERFACE_MODE_RMII:
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val = GPR_ENET_QOS_INTF_SEL_RMII;
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val |= (dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL);
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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val = GPR_ENET_QOS_INTF_SEL_RGMII |
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GPR_ENET_QOS_RGMII_EN;
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break;
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default:
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pr_debug("imx dwmac doesn't support %s interface\n",
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phy_modes(plat_dat->phy_interface));
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return -EINVAL;
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}
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val = FIELD_PREP(GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) |
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GPR_ENET_QOS_CLK_GEN_EN;
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if (phy_intf_sel == PHY_INTF_SEL_RMII && !dwmac->rmii_refclk_ext)
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val |= GPR_ENET_QOS_CLK_TX_CLK_SEL;
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else if (phy_intf_sel == PHY_INTF_SEL_RGMII)
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val |= GPR_ENET_QOS_RGMII_EN;
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val |= GPR_ENET_QOS_CLK_GEN_EN;
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return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
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GPR_ENET_QOS_INTF_MODE_MASK, val);
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};
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static int
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imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat)
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imx8dxl_set_intf_mode(struct imx_priv_data *dwmac, u8 phy_intf_sel)
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{
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int ret = 0;
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/* TBD: depends on imx8dxl scu interfaces to be upstreamed */
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return ret;
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return 0;
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}
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static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat)
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static int imx93_set_intf_mode(struct imx_priv_data *dwmac, u8 phy_intf_sel)
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{
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struct imx_priv_data *dwmac = plat_dat->bsp_priv;
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int val, ret;
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unsigned int val;
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int ret;
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switch (plat_dat->phy_interface) {
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case PHY_INTERFACE_MODE_MII:
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val = MX93_GPR_ENET_QOS_INTF_SEL_MII;
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break;
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case PHY_INTERFACE_MODE_RMII:
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if (dwmac->rmii_refclk_ext) {
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ret = regmap_clear_bits(dwmac->intf_regmap,
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dwmac->intf_reg_off +
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MX93_GPR_CLK_SEL_OFFSET,
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MX93_GPR_ENET_QOS_CLK_SEL_MASK);
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if (ret)
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return ret;
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}
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val = MX93_GPR_ENET_QOS_INTF_SEL_RMII;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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val = MX93_GPR_ENET_QOS_INTF_SEL_RGMII;
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break;
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default:
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dev_dbg(dwmac->dev, "imx dwmac doesn't support %s interface\n",
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phy_modes(plat_dat->phy_interface));
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return -EINVAL;
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if (phy_intf_sel == PHY_INTF_SEL_RMII && dwmac->rmii_refclk_ext) {
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ret = regmap_clear_bits(dwmac->intf_regmap,
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dwmac->intf_reg_off +
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MX93_GPR_CLK_SEL_OFFSET,
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MX93_GPR_ENET_QOS_CLK_SEL_MASK);
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if (ret)
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return ret;
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}
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val |= MX93_GPR_ENET_QOS_CLK_GEN_EN;
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val = FIELD_PREP(MX93_GPR_ENET_QOS_INTF_SEL_MASK, phy_intf_sel) |
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MX93_GPR_ENET_QOS_CLK_GEN_EN;
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return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
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MX93_GPR_ENET_QOS_INTF_MODE_MASK, val);
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};
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@ -170,34 +134,24 @@ static int imx_dwmac_clks_config(void *priv, bool enabled)
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return ret;
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}
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static int imx_dwmac_init(struct platform_device *pdev, void *priv)
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static int imx_set_phy_intf_sel(void *bsp_priv, u8 phy_intf_sel)
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{
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struct plat_stmmacenet_data *plat_dat;
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struct imx_priv_data *dwmac = priv;
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int ret;
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struct imx_priv_data *dwmac = bsp_priv;
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plat_dat = dwmac->plat_dat;
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if (!dwmac->ops->set_intf_mode)
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return 0;
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if (dwmac->ops->set_intf_mode) {
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ret = dwmac->ops->set_intf_mode(plat_dat);
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if (ret)
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return ret;
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}
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if (phy_intf_sel != PHY_INTF_SEL_GMII_MII &&
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phy_intf_sel != PHY_INTF_SEL_RGMII &&
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phy_intf_sel != PHY_INTF_SEL_RMII)
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return -EINVAL;
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return 0;
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}
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static void imx_dwmac_exit(struct platform_device *pdev, void *priv)
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{
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/* nothing to do now */
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return dwmac->ops->set_intf_mode(dwmac, phy_intf_sel);
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}
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static int imx_dwmac_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i,
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phy_interface_t interface, int speed)
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{
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struct imx_priv_data *dwmac = bsp_priv;
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interface = dwmac->plat_dat->phy_interface;
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if (interface == PHY_INTERFACE_MODE_RMII ||
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interface == PHY_INTERFACE_MODE_MII)
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return 0;
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@ -244,8 +198,8 @@ static void imx93_dwmac_fix_speed(void *priv, int speed, unsigned int mode)
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if (regmap_read(dwmac->intf_regmap, dwmac->intf_reg_off, &iface))
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return;
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iface &= MX93_GPR_ENET_QOS_INTF_MASK;
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if (iface != MX93_GPR_ENET_QOS_INTF_SEL_RGMII)
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if (FIELD_GET(MX93_GPR_ENET_QOS_INTF_SEL_MASK, iface) !=
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PHY_INTF_SEL_RGMII)
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return;
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old_ctrl = readl(dwmac->base_addr + MAC_CTRL_REG);
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@ -258,6 +212,7 @@ static void imx93_dwmac_fix_speed(void *priv, int speed, unsigned int mode)
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readl(dwmac->base_addr + MAC_CTRL_REG);
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usleep_range(10, 20);
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iface &= MX93_GPR_ENET_QOS_INTF_SEL_MASK;
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iface |= MX93_GPR_ENET_QOS_CLK_GEN_EN;
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regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
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MX93_GPR_ENET_QOS_INTF_MODE_MASK, iface);
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@ -370,8 +325,7 @@ static int imx_dwmac_probe(struct platform_device *pdev)
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plat_dat->tx_queues_cfg[i].tbs_en = 1;
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plat_dat->host_dma_width = dwmac->ops->addr_width;
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plat_dat->init = imx_dwmac_init;
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plat_dat->exit = imx_dwmac_exit;
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plat_dat->set_phy_intf_sel = imx_set_phy_intf_sel;
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plat_dat->clks_config = imx_dwmac_clks_config;
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plat_dat->bsp_priv = dwmac;
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dwmac->plat_dat = plat_dat;
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@ -24,10 +24,10 @@
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#define GMAC_INTF_RATE_125M 125000000 /* 125MHz */
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/* SoC PHY interface control register */
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#define PHY_INTF_SEL_MII 0x00
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#define PHY_INTF_SEL_SGMII 0x01
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#define PHY_INTF_SEL_RGMII 0x02
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#define PHY_INTF_SEL_RMII 0x08
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#define S32_PHY_INTF_SEL_MII 0x00
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#define S32_PHY_INTF_SEL_SGMII 0x01
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#define S32_PHY_INTF_SEL_RGMII 0x02
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#define S32_PHY_INTF_SEL_RMII 0x08
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struct s32_priv_data {
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void __iomem *ioaddr;
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@ -40,7 +40,7 @@ struct s32_priv_data {
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static int s32_gmac_write_phy_intf_select(struct s32_priv_data *gmac)
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{
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writel(PHY_INTF_SEL_RGMII, gmac->ctrl_sts);
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writel(S32_PHY_INTF_SEL_RGMII, gmac->ctrl_sts);
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dev_dbg(gmac->dev, "PHY mode set to %s\n", phy_modes(*gmac->intf_mode));
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@ -396,6 +396,7 @@ void stmmac_ptp_register(struct stmmac_priv *priv);
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void stmmac_ptp_unregister(struct stmmac_priv *priv);
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int stmmac_xdp_open(struct net_device *dev);
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void stmmac_xdp_release(struct net_device *dev);
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int stmmac_get_phy_intf_sel(phy_interface_t interface);
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int stmmac_resume(struct device *dev);
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int stmmac_suspend(struct device *dev);
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void stmmac_dvr_remove(struct device *dev);
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@ -3082,6 +3082,56 @@ static void stmmac_check_ether_addr(struct stmmac_priv *priv)
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}
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}
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int stmmac_get_phy_intf_sel(phy_interface_t interface)
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{
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int phy_intf_sel = -EINVAL;
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if (interface == PHY_INTERFACE_MODE_MII ||
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interface == PHY_INTERFACE_MODE_GMII)
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phy_intf_sel = PHY_INTF_SEL_GMII_MII;
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else if (phy_interface_mode_is_rgmii(interface))
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phy_intf_sel = PHY_INTF_SEL_RGMII;
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else if (interface == PHY_INTERFACE_MODE_SGMII)
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phy_intf_sel = PHY_INTF_SEL_SGMII;
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else if (interface == PHY_INTERFACE_MODE_RMII)
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phy_intf_sel = PHY_INTF_SEL_RMII;
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else if (interface == PHY_INTERFACE_MODE_REVMII)
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phy_intf_sel = PHY_INTF_SEL_REVMII;
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return phy_intf_sel;
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}
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EXPORT_SYMBOL_GPL(stmmac_get_phy_intf_sel);
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static int stmmac_prereset_configure(struct stmmac_priv *priv)
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{
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struct plat_stmmacenet_data *plat_dat = priv->plat;
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phy_interface_t interface;
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int phy_intf_sel, ret;
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if (!plat_dat->set_phy_intf_sel)
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return 0;
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interface = plat_dat->phy_interface;
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phy_intf_sel = stmmac_get_phy_intf_sel(interface);
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if (phy_intf_sel < 0) {
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netdev_err(priv->dev,
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"failed to get phy_intf_sel for %s: %pe\n",
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phy_modes(interface), ERR_PTR(phy_intf_sel));
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return phy_intf_sel;
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}
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ret = plat_dat->set_phy_intf_sel(plat_dat->bsp_priv, phy_intf_sel);
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if (ret == -EINVAL)
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netdev_err(priv->dev, "platform does not support %s\n",
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phy_modes(interface));
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else if (ret < 0)
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netdev_err(priv->dev,
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"platform failed to set interface %s: %pe\n",
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phy_modes(interface), ERR_PTR(ret));
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return ret;
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}
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/**
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* stmmac_init_dma_engine - DMA init.
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* @priv: driver private structure
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@ -3108,6 +3158,10 @@ static int stmmac_init_dma_engine(struct stmmac_priv *priv)
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if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
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priv->plat->dma_cfg->atds = 1;
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ret = stmmac_prereset_configure(priv);
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if (ret)
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return ret;
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ret = stmmac_reset(priv, priv->ioaddr);
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if (ret) {
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netdev_err(priv->dev, "Failed to reset the dma\n");
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@ -250,6 +250,7 @@ struct plat_stmmacenet_data {
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struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
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void (*get_interfaces)(struct stmmac_priv *priv, void *bsp_priv,
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unsigned long *interfaces);
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int (*set_phy_intf_sel)(void *priv, u8 phy_intf_sel);
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int (*set_clk_tx_rate)(void *priv, struct clk *clk_tx_i,
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phy_interface_t interface, int speed);
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void (*fix_mac_speed)(void *priv, int speed, unsigned int mode);
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