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ice: dpll: fix misplaced header macros

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The CGU register definitions (ICE_CGU_R10, ICE_CGU_R11 and related field
masks) were placed after the #endif of the _ICE_DPLL_H_ include guard,
leaving them unprotected. Move them inside the guard.

Fixes: ad1df4f2d5 ("ice: dpll: Support E825-C SyncE and dynamic pin discovery")
Signed-off-by: Ivan Vecera <ivecera@redhat.com>
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Link: https://patch.msgid.link/20260506-jk-iwl-net-2026-05-04-v2-8-a5ea4dc837a9@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Ivan Vecera 2026-05-06 14:48:17 -07:00 committed by Jakub Kicinski
parent cce709d8df
commit 30f1658fc5
1 changed files with 16 additions and 16 deletions
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32
drivers/net/ethernet/intel/ice/ice_dpll.h
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@ -8,6 +8,22 @@
#define ICE_DPLL_RCLK_NUM_MAX 4
#define ICE_CGU_R10 0x28
#define ICE_CGU_R10_SYNCE_CLKO_SEL GENMASK(8, 5)
#define ICE_CGU_R10_SYNCE_CLKODIV_M1 GENMASK(13, 9)
#define ICE_CGU_R10_SYNCE_CLKODIV_LOAD BIT(14)
#define ICE_CGU_R10_SYNCE_DCK_RST BIT(15)
#define ICE_CGU_R10_SYNCE_ETHCLKO_SEL GENMASK(18, 16)
#define ICE_CGU_R10_SYNCE_ETHDIV_M1 GENMASK(23, 19)
#define ICE_CGU_R10_SYNCE_ETHDIV_LOAD BIT(24)
#define ICE_CGU_R10_SYNCE_DCK2_RST BIT(25)
#define ICE_CGU_R10_SYNCE_S_REF_CLK GENMASK(31, 27)
#define ICE_CGU_R11 0x2C
#define ICE_CGU_R11_SYNCE_S_BYP_CLK GENMASK(6, 1)
#define ICE_CGU_BYPASS_MUX_OFFSET_E825C 3
/**
* enum ice_dpll_pin_sw - enumerate ice software pin indices:
* @ICE_DPLL_PIN_SW_1_IDX: index of first SW pin
@ -157,19 +173,3 @@ static inline void ice_dpll_deinit(struct ice_pf *pf) { }
#endif
#endif
#define ICE_CGU_R10 0x28
#define ICE_CGU_R10_SYNCE_CLKO_SEL GENMASK(8, 5)
#define ICE_CGU_R10_SYNCE_CLKODIV_M1 GENMASK(13, 9)
#define ICE_CGU_R10_SYNCE_CLKODIV_LOAD BIT(14)
#define ICE_CGU_R10_SYNCE_DCK_RST BIT(15)
#define ICE_CGU_R10_SYNCE_ETHCLKO_SEL GENMASK(18, 16)
#define ICE_CGU_R10_SYNCE_ETHDIV_M1 GENMASK(23, 19)
#define ICE_CGU_R10_SYNCE_ETHDIV_LOAD BIT(24)
#define ICE_CGU_R10_SYNCE_DCK2_RST BIT(25)
#define ICE_CGU_R10_SYNCE_S_REF_CLK GENMASK(31, 27)
#define ICE_CGU_R11 0x2C
#define ICE_CGU_R11_SYNCE_S_BYP_CLK GENMASK(6, 1)
#define ICE_CGU_BYPASS_MUX_OFFSET_E825C 3