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wifi: ath12k: Add support to clear qdesc array in REO cache

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Currently, the existing code lacks functionality to clear the qdesc
array in the REO cache. As a result, any updates in the LUT are not
reflected in the REO cache. To address this issue, add functionality
to clear the qdesc array in the REO cache during a peer TID update.
To do this, set the CLEAR_DESC_ARRAY field of
WCSS_UMAC_REO_R0_QDESC_ADDR_READ and then reset it.

Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.3.1-00173-QCAHKSWPL_SILICONZ-1

Signed-off-by: Balamurugan S <quic_bselvara@quicinc.com>
Signed-off-by: Nithyanantham Paramasivam <quic_nithp@quicinc.com>
Reviewed-by: Vasanthakumar Thiagarajan <vasanthakumar.thiagarajan@oss.qualcomm.com>
Link: https://patch.msgid.link/20250402152529.1649402-3-quic_nithp@quicinc.com
Signed-off-by: Jeff Johnson <jeff.johnson@oss.qualcomm.com>
This commit is contained in:
Balamurugan S 2025-04-02 20:55:28 +05:30 committed by Jeff Johnson
parent 0bbcd42b15
commit 30b03edd26
3 changed files with 20 additions and 1 deletions
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1
drivers/net/wireless/ath/ath12k/dp_rx.c
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@ -762,6 +762,7 @@ static void ath12k_peer_rx_tid_qref_setup(struct ath12k_base *ab, u16 peer_id, u
qref->info1 = u32_encode_bits(upper_32_bits(paddr),
BUFFER_ADDR_INFO1_ADDR) |
u32_encode_bits(tid, DP_REO_QREF_NUM);
ath12k_hal_reo_shared_qaddr_cache_clear(ab);
}
static void ath12k_peer_rx_tid_qref_reset(struct ath12k_base *ab, u16 peer_id, u16 tid)

1
drivers/net/wireless/ath/ath12k/hal.h
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@ -1172,4 +1172,5 @@ int ath12k_hal_srng_update_shadow_config(struct ath12k_base *ab,
void ath12k_hal_srng_shadow_config(struct ath12k_base *ab);
void ath12k_hal_srng_shadow_update_hp_tp(struct ath12k_base *ab,
struct hal_srng *srng);
void ath12k_hal_reo_shared_qaddr_cache_clear(struct ath12k_base *ab);
#endif

19
drivers/net/wireless/ath/ath12k/hal_rx.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: BSD-3-Clause-Clear
/*
* Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "debug.h"
@ -851,3 +851,20 @@ void ath12k_hal_reo_hw_setup(struct ath12k_base *ab, u32 ring_hash_map)
ath12k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3,
ring_hash_map);
}
void ath12k_hal_reo_shared_qaddr_cache_clear(struct ath12k_base *ab)
{
u32 val;
lockdep_assert_held(&ab->base_lock);
val = ath12k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_REO_REG +
HAL_REO1_QDESC_ADDR(ab));
val |= u32_encode_bits(1, HAL_REO_QDESC_ADDR_READ_CLEAR_QDESC_ARRAY);
ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG +
HAL_REO1_QDESC_ADDR(ab), val);
val &= ~HAL_REO_QDESC_ADDR_READ_CLEAR_QDESC_ARRAY;
ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG +
HAL_REO1_QDESC_ADDR(ab), val);
}