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mmc: sdhci-esdhc-imx: verify tuning control status after configuration
Enhance manual tuning configuration reliability by adding tuning control status checks per the i.MX Reference Manual recommendations. Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20250409075550.3413032-6-ziniu.wang_1@nxp.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -83,6 +83,7 @@
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#define ESDHC_TUNE_CTRL_STEP 1
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#define ESDHC_TUNE_CTRL_MIN 0
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#define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
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#define ESDHC_TUNE_CTRL_STATUS_TAP_SEL_MASK GENMASK(30, 16)
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#define ESDHC_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK GENMASK(30, 24)
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#define ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK GENMASK(14, 8)
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#define ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK GENMASK(7, 4)
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@ -1213,7 +1214,7 @@ static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
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{
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int min, max, avg, ret;
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int win_length, target_min, target_max, target_win_length;
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u32 clk_tune_ctrl_status;
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u32 clk_tune_ctrl_status, temp;
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min = ESDHC_TUNE_CTRL_MIN;
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max = ESDHC_TUNE_CTRL_MIN;
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@ -1269,6 +1270,13 @@ static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
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ESDHC_AUTO_TUNING_WINDOW);
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writel(clk_tune_ctrl_status, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
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ret = readl_poll_timeout(host->ioaddr + ESDHC_TUNE_CTRL_STATUS, temp,
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clk_tune_ctrl_status ==
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FIELD_GET(ESDHC_TUNE_CTRL_STATUS_TAP_SEL_MASK, temp),
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1, 10);
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if (ret == -ETIMEDOUT)
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dev_warn(mmc_dev(host->mmc),
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"clock tuning control status not set in 10us\n");
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ret = mmc_send_tuning(host->mmc, opcode, NULL);
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esdhc_post_tuning(host);
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