github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-05-22 14:12:07 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

Samsung DTS ARM64 changes for v7.1

Browse Source 
1. Add initial support for Axis ARTPEC-9 SoC and Alfred board using it.
    Just like ARTPEC-8, this is a derivative of Samsung Exynos SoC made
    for Axis, sharing most or all of core SoC blocks with Samsung
    designs.
 
 2. New boards: Exynos7870 based Samsung Galaxy J7 (2016) and Samsung
    Galaxy J5 (2017).
 
 3. Google GS101 Pixel phone: describe all PMIC regulators and Maxim
    fuel-gauge.
 
 4. ExynosAutov920: add G3D (GPU) clock controller (CMU).
 -----BEGIN PGP SIGNATURE-----
 
 iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmnCigYQHGtyemtAa2Vy
 bmVsLm9yZwAKCRDBN2bmhouD18c4D/0TKjfH5YBXJlaCOIXVwV1BfFteQLFr9Vhn
 CKVpvs/SAaB8Z3Mh9m4L12b/gACufB6Nm0I4y1wyuA/f90dXt918ntcAm+l0fpcu
 VpsOitkHNOXE/+JMyr/7sg8BkS0oU9geLfn68c1JxdvzsE5tTOEPM3wtz0GfhX61
 S1QyUtwyjufvGgVLXP6hkDySj2a9oAnWYxCo30Y+m0D4RrXVzW/rAq+dHTIf4Fep
 N9bOeyYyLO8TCDbn4K8i80QxUjh08u3QfFNxjRg9YjOE4giAaRXVku5erWT90Xkx
 8Oq15FGLUv7LdfKvF8upqGgYfC7v0muMV2wCwHflIwaWcKHheWRKNGpKuwm+E3nl
 k3pTIen881u1cfUZK2LL4nW+yKSBXnLhEeX1oY+/dShbjvr0ys6ExCTtpMRl5uP/
 RczYYKCHeaU/P2mlkM9UNdhdNHs0XA1kN1sqkAe5bZ9il9XLb14ypPQuSez6nTtx
 IQp6PrAY8BegzKHzxLf3fOZulhk4SQXc4nncPwEc2V84gf427h6O6otM64WAbALw
 2y7MZdSHCpRqx6VEX57Fnow+IQrUHo+sGZ7r9rlXwv9ZOR9KG/h6KD641c2yCKdn
 vMC/8rr7hpaTJZMK+qmNFaVLE0ruKSWMkWXaI3AwR2CYwYn75RP0PKAPBeY895j5
 c491yJQTtg==
 =HJ88
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmnNTHwACgkQmmx57+YA
 GNl1ug//cuB2QN6wisF+aZLHFaPmdh/Z18iRYJAMzxy1ZLUouec9dXovIFNUjXE1
 8UXzhnmAjgUge4LtKm1pJeW49kcmWPjR534u0XqXVDM/dIHMi6sSWmcPwTDQBti7
 +oWLN81CKs+NH5E8xeTmuSSLguIkeyhpUY1YFOULMird8bIoQJ2wElZVYnapfyTy
 c4lazly7tNNCVvbTeRyLjW8CSvSae9o/ykfv53sqao3kQWK1t8fy9ldIuVwBO9oG
 KYKNaiztCQyki7OKMNze1pwmtCd9dQejVoQo1oIgYeHVQYbv5fIKfiJ3dsQRs1JD
 rWzuYdbRoIBKDbSc/iDXVZd1ZIMML891onS94JsFICImbJjC0pglT5oaAQ0FU2qe
 A9P2UnVP6SyUjRRmtKpAk2uJNuMYyrFarFvt13MWG6N9abYiSOx7+jGr30427jvz
 AeF1n0ub8ZqGw2JozZgRsPfVkHiwcItwtiE5L7Hy8l0kDzvAg1bNfvPlPeDRqstP
 UAdZsGL34C1YHm6r6h1tW2E8h85Qf2mPYTDWAVk/rMFxn8E4Vj3H3h/KZNJmWYXZ
 KAsSc8u1QZW+hIrRhdoW/yFBldWyy3tHiIRPdsy/sTlfo6epwEOiiNTv3Gu8JFWV
 t4Tj1lqKHYDdhKBls6v0gpim5p+4/3/EZaVK5F8y9aKOGQVADG8=
 =2rdh
 -----END PGP SIGNATURE-----

Merge tag 'samsung-dt64-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt

Samsung DTS ARM64 changes for v7.1

1. Add initial support for Axis ARTPEC-9 SoC and Alfred board using it.
   Just like ARTPEC-8, this is a derivative of Samsung Exynos SoC made
   for Axis, sharing most or all of core SoC blocks with Samsung
   designs.

2. New boards: Exynos7870 based Samsung Galaxy J7 (2016) and Samsung
   Galaxy J5 (2017).

3. Google GS101 Pixel phone: describe all PMIC regulators and Maxim
   fuel-gauge.

4. ExynosAutov920: add G3D (GPU) clock controller (CMU).

* tag 'samsung-dt64-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: dts: exynos8895: Move I2C address/size-cells to DTSI
  arm64: dts: exynos7870: Move I2C address/size-cells to DTSI
  arm64: dts: exynos: gs101-pixel-common: add Maxim MAX77759 fuel gauge
  arm64: dts: exynos: add initial support for Samsung Galaxy J5
  dt-bindings: arm: samsung: add compatible for samsung-j5y17lte
  arm64: dts: exynosautov920: add CMU_G3D clock DT nodes
  arm64: dts: exynos: gs101-pixel: add all S2MPG1x regulators
  arm64: dts: exynos: add initial support for Samsung Galaxy J7 (2016)
  dt-bindings: arm: samsung: add compatible for samsung-j7xelte
  arm64: dts: axis: artpec9: Fix missing soc unit address
  arm64: dts: axis: Add ARTPEC-9 Alfred board support
  arm64: dts: exynos: axis: Add initial ARTPEC-9 SoC support
  dt-bindings: arm: axis: Add ARTPEC-9 alfred board
  dt-bindings: clock: Add ARTPEC-9 clock controller

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2026-04-01 18:34:43 +02:00
commit 2feb6df85c
21 changed files with 2640 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/devicetree/bindings/arm/axis.yaml
View File

@ -31,6 +31,12 @@ properties:
- axis,artpec8-grizzly
- const: axis,artpec8
- description: Axis ARTPEC-9 SoC board
items:
- enum:
- axis,artpec9-alfred
- const: axis,artpec9
additionalProperties: true
...

2
Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
View File

@ -216,7 +216,9 @@ properties:
items:
- enum:
- samsung,a2corelte # Samsung Galaxy A2 Core
- samsung,j5y17lte # Samsung Galaxy J5 (2017)
- samsung,j6lte # Samsung Galaxy J6
- samsung,j7xelte # Samsung Galaxy J7 (2016)
- samsung,on7xelte # Samsung Galaxy J7 Prime
- const: samsung,exynos7870

232
Documentation/devicetree/bindings/clock/axis,artpec9-clock.yaml Normal file
View File

@ -0,0 +1,232 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/axis,artpec9-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Axis ARTPEC-9 SoC clock controller
maintainers:
- Jesper Nilsson <jesper.nilsson@axis.com>
description: |
ARTPEC-9 clock controller is comprised of several CMU (Clock Management Unit)
units, generating clocks for different domains. Those CMU units are modeled
as separate device tree nodes, and might depend on each other.
The root clock in that root tree is an external clock: OSCCLK (25 MHz).
This external clock must be defined as a fixed-rate clock in dts.
CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and
dividers, all other clocks of function blocks (other CMUs) are usually
derived from CMU_CMU.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All clocks available for usage
in clock consumer nodes are defined as preprocessor macros in
'include/dt-bindings/clock/axis,artpec9-clk.h' header.
properties:
compatible:
enum:
- axis,artpec9-cmu-cmu
- axis,artpec9-cmu-bus
- axis,artpec9-cmu-core
- axis,artpec9-cmu-cpucl
- axis,artpec9-cmu-fsys0
- axis,artpec9-cmu-fsys1
- axis,artpec9-cmu-imem
- axis,artpec9-cmu-peri
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 5
clock-names:
minItems: 1
maxItems: 5
"#clock-cells":
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- "#clock-cells"
allOf:
- if:
properties:
compatible:
const: axis,artpec9-cmu-cmu
then:
properties:
clocks:
items:
- description: External reference clock (25 MHz)
clock-names:
items:
- const: fin_pll
- if:
properties:
compatible:
const: axis,artpec9-cmu-bus
then:
properties:
clocks:
items:
- description: External reference clock (25 MHz)
- description: CMU_BUS bus clock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: bus
- if:
properties:
compatible:
const: axis,artpec9-cmu-core
then:
properties:
clocks:
items:
- description: External reference clock (25 MHz)
- description: CMU_CORE main clock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: main
- if:
properties:
compatible:
const: axis,artpec9-cmu-cpucl
then:
properties:
clocks:
items:
- description: External reference clock (25 MHz)
- description: CMU_CPUCL switch clock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: switch
- if:
properties:
compatible:
const: axis,artpec9-cmu-fsys0
then:
properties:
clocks:
items:
- description: External reference clock (25 MHz)
- description: CMU_FSYS0 bus clock (from CMU_CMU)
- description: CMU_FSYS0 IP clock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: bus
- const: ip
- if:
properties:
compatible:
const: axis,artpec9-cmu-fsys1
then:
properties:
clocks:
items:
- description: External reference clock (25 MHz)
- description: CMU_FSYS1 scan0 clock (from CMU_CMU)
- description: CMU_FSYS1 scan1 clock (from CMU_CMU)
- description: CMU_FSYS1 bus clock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: scan0
- const: scan1
- const: bus
- if:
properties:
compatible:
const: axis,artpec9-cmu-imem
then:
properties:
clocks:
items:
- description: External reference clock (25 MHz)
- description: CMU_IMEM ACLK clock (from CMU_CMU)
- description: CMU_IMEM CA5 clock (from CMU_CMU)
- description: CMU_IMEM JPEG clock (from CMU_CMU)
- description: CMU_IMEM SSS clock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: aclk
- const: ca5
- const: jpeg
- const: sss
- if:
properties:
compatible:
const: axis,artpec9-cmu-peri
then:
properties:
clocks:
items:
- description: External reference clock (25 MHz)
- description: CMU_PERI IP clock (from CMU_CMU)
- description: CMU_PERI DISP clock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: ip
- const: disp
additionalProperties: false
examples:
# Clock controller node for CMU_FSYS1
- |
#include <dt-bindings/clock/axis,artpec9-clk.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
cmu_fsys1: clock-controller@14c10000 {
compatible = "axis,artpec9-cmu-fsys1";
reg = <0x0 0x14c10000 0x0 0x4000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN0>,
<&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN1>,
<&cmu_cmu CLK_DOUT_CMU_FSYS1_BUS>;
clock-names = "fin_pll", "scan0", "scan1", "bus";
};
};
...

2
arch/arm64/boot/dts/exynos/Makefile
View File

@ -8,7 +8,9 @@ dtb-$(CONFIG_ARCH_EXYNOS) += \
exynos5433-tm2e.dtb \
exynos7-espresso.dtb \
exynos7870-a2corelte.dtb \
exynos7870-j5y17lte.dtb \
exynos7870-j6lte.dtb \
exynos7870-j7xelte.dtb \
exynos7870-on7xelte.dtb \
exynos7885-jackpotlte.dtb \
exynos850-e850-96.dtb \

3
arch/arm64/boot/dts/exynos/axis/Makefile
View File

@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ARTPEC) += \
artpec8-grizzly.dtb
artpec8-grizzly.dtb \
artpec9-alfred.dtb

36
arch/arm64/boot/dts/exynos/axis/artpec9-alfred.dts Normal file
View File

@ -0,0 +1,36 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Axis ARTPEC-9 Alfred board device tree source
*
* Copyright (c) 2025 Samsung Electronics Co., Ltd.
* https://www.samsung.com
* Copyright (c) 2025 Axis Communications AB.
* https://www.axis.com
*/
/dts-v1/;
#include "artpec9.dtsi"
#include "artpec9-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "ARTPEC-9 alfred board";
compatible = "axis,artpec9-alfred", "axis,artpec9";
aliases {
serial0 = &serial_0;
};
chosen {
stdout-path = &serial_0;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
};
&osc_clk {
clock-frequency = <50000000>;
};

115
arch/arm64/boot/dts/exynos/axis/artpec9-pinctrl.dtsi Normal file
View File

@ -0,0 +1,115 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Axis ARTPEC-9 SoC pin-mux and pin-config device tree source
*
* Copyright (c) 2025 Samsung Electronics Co., Ltd.
* https://www.samsung.com
* Copyright (c) 2025 Axis Communications AB.
* https://www.axis.com
*/
#include "artpec-pinctrl.h"
&pinctrl_fsys0 {
gpe0: gpe0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpe1: gpe1-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpe2: gpe2-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpe3: gpe3-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpe4: gpe4-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf0: gpf0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf1: gpf1-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpi0: gpi0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gps0: gps0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gps1: gps1-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
&pinctrl_fsys1 {
gpu0: gpu0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
serial0_bus: serial0-bus-pins {
samsung,pins = "gpu0-0", "gpu0-1";
samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
};
};
&pinctrl_peric {
gpa0: gpa0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpa1: gpa1-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};

277
arch/arm64/boot/dts/exynos/axis/artpec9.dtsi Normal file
View File

@ -0,0 +1,277 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Axis ARTPEC-9 SoC device tree source
*
* Copyright (c) 2025 Samsung Electronics Co., Ltd.
* https://www.samsung.com
* Copyright (c) 2025 Axis Communications AB.
* https://www.axis.com
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/axis,artpec9-clk.h>
/ {
compatible = "axis,artpec9";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
pinctrl0 = &pinctrl_fsys0;
pinctrl1 = &pinctrl_fsys1;
pinctrl2 = &pinctrl_peric;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0>;
enable-method = "psci";
cpu-idle-states = <&cpu_sleep>;
clocks = <&cmu_cpucl CLK_GOUT_CPUCL_CLUSTER_CPU>;
clock-names = "cpu";
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x100>;
enable-method = "psci";
cpu-idle-states = <&cpu_sleep>;
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x200>;
enable-method = "psci";
cpu-idle-states = <&cpu_sleep>;
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x300>;
enable-method = "psci";
cpu-idle-states = <&cpu_sleep>;
};
cpu4: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x400>;
enable-method = "psci";
cpu-idle-states = <&cpu_sleep>;
};
cpu5: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x500>;
enable-method = "psci";
cpu-idle-states = <&cpu_sleep>;
};
idle-states {
entry-method = "psci";
cpu_sleep: cpu-sleep {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <300>;
exit-latency-us = <1200>;
min-residency-us = <2000>;
};
};
};
fin_pll: clock-finpll {
compatible = "fixed-factor-clock";
clocks = <&osc_clk>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clock-output-names = "fin_pll";
};
osc_clk: clock-osc {
/* XXTI */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "osc_clk";
};
pmu {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
soc: soc@0 {
compatible = "simple-bus";
ranges = <0x0 0x0 0x0 0x0 0x0 0x17000000>;
#address-cells = <2>;
#size-cells = <2>;
cmu_imem: clock-controller@10010000 {
compatible = "axis,artpec9-cmu-imem";
reg = <0x0 0x10010000 0x0 0x4000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&cmu_cmu CLK_DOUT_CMU_IMEM_ACLK>,
<&cmu_cmu CLK_DOUT_CMU_IMEM_CA5>,
<&cmu_cmu CLK_DOUT_CMU_IMEM_JPEG>,
<&cmu_cmu CLK_DOUT_CMU_IMEM_SSS>;
clock-names = "fin_pll", "aclk", "ca5", "jpeg", "sss";
};
timer@10040000 {
compatible = "axis,artpec9-mct", "samsung,exynos4210-mct";
reg = <0x0 0x10040000 0x0 0x1000>;
clocks = <&fin_pll>, <&cmu_imem CLK_GOUT_IMEM_MCT0_PCLK>;
clock-names = "fin_pll", "mct";
interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@10400000 {
compatible = "arm,gic-v3";
reg = <0x0 0x10400000 0x0 0x00040000>,
<0x0 0x10440000 0x0 0x000c0000>;
#interrupt-cells = <3>;
interrupt-controller;
redistributor-stride = <0x0 0x20000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
cmu_cpucl: clock-controller@12810000 {
compatible = "axis,artpec9-cmu-cpucl";
reg = <0x0 0x12810000 0x0 0x4000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&cmu_cmu CLK_DOUT_CMU_CPUCL_SWITCH>;
clock-names = "fin_pll", "switch";
};
cmu_cmu: clock-controller@12c00000 {
compatible = "axis,artpec9-cmu-cmu";
reg = <0x0 0x12c00000 0x0 0x4000>;
#clock-cells = <1>;
clocks = <&fin_pll>;
clock-names = "fin_pll";
};
cmu_core: clock-controller@12c10000 {
compatible = "axis,artpec9-cmu-core";
reg = <0x0 0x12c10000 0x0 0x4000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&cmu_cmu CLK_DOUT_CMU_CORE_MAIN>;
clock-names = "fin_pll", "main";
};
cmu_bus: clock-controller@13410000 {
compatible = "axis,artpec9-cmu-bus";
reg = <0x0 0x13410000 0x0 0x4000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&cmu_cmu CLK_DOUT_CMU_BUS>;
clock-names = "fin_pll", "bus";
};
cmu_peri: clock-controller@14010000 {
compatible = "axis,artpec9-cmu-peri";
reg = <0x0 0x14010000 0x0 0x4000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&cmu_cmu CLK_DOUT_CMU_PERI_IP>,
<&cmu_cmu CLK_DOUT_CMU_PERI_DISP>;
clock-names = "fin_pll", "ip", "disp";
};
pinctrl_peric: pinctrl@141f0000 {
compatible = "axis,artpec9-pinctrl";
reg = <0x0 0x141f0000 0x0 0x1000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
};
cmu_fsys0: clock-controller@14410000 {
compatible = "axis,artpec9-cmu-fsys0";
reg = <0x0 0x14410000 0x0 0x4000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&cmu_cmu CLK_DOUT_CMU_FSYS0_BUS>,
<&cmu_cmu CLK_DOUT_CMU_FSYS0_IP>;
clock-names = "fin_pll", "bus", "ip";
};
pinctrl_fsys0: pinctrl@14430000 {
compatible = "axis,artpec9-pinctrl";
reg = <0x0 0x14430000 0x0 0x1000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
};
cmu_fsys1: clock-controller@14c10000 {
compatible = "axis,artpec9-cmu-fsys1";
reg = <0x0 0x14c10000 0x0 0x4000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN0>,
<&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN1>,
<&cmu_cmu CLK_DOUT_CMU_FSYS1_BUS>;
clock-names = "fin_pll", "scan0", "scan1", "bus";
};
pinctrl_fsys1: pinctrl@14c30000 {
compatible = "axis,artpec9-pinctrl";
reg = <0x0 0x14c30000 0x0 0x1000>;
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
};
pmu_system_controller: system-controller@14c40000 {
compatible = "axis,artpec9-pmu", "samsung,exynos7-pmu", "syscon";
reg = <0x0 0x14c40000 0x0 0x10000>;
};
serial_0: serial@14c70000 {
compatible = "axis,artpec9-uart", "samsung,exynos8895-uart";
reg = <0x0 0x14c70000 0x0 0x100>;
clocks = <&cmu_fsys1 CLK_GOUT_FSYS1_UART0_PCLK>,
<&cmu_fsys1 CLK_GOUT_FSYS1_UART0_SCLK_UART>;
clock-names = "uart", "clk_uart_baud0";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&serial0_bus>;
samsung,uart-fifosize = <64>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};

9
arch/arm64/boot/dts/exynos/exynos7870-a2corelte.dts
View File

@ -158,9 +158,6 @@ &gpu {
};
&hsi2c0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pmic@66 {
@ -394,9 +391,6 @@ vdd_ldo35: ldo35 {
};
&i2c5 {
#address-cells = <1>;
#size-cells = <0>;
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <400000>;
@ -428,9 +422,6 @@ proximity@48 {
};
&i2c6 {
#address-cells = <1>;
#size-cells = <0>;
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <400000>;

523
arch/arm64/boot/dts/exynos/exynos7870-j5y17lte.dts Normal file
View File

@ -0,0 +1,523 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Samsung Galaxy J5 (2017) (j5y17lte) device tree source
*
* Copyright (c) 2024 Andras Sebok <sebokandris2009@gmail.com>
*/
/dts-v1/;
#include "exynos7870.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "Samsung Galaxy J5 (2017)";
compatible = "samsung,j5y17lte", "samsung,exynos7870";
chassis-type = "handset";
aliases {
mmc0 = &mmc0;
mmc1 = &mmc1;
mmc2 = &mmc2;
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
};
chosen {
#address-cells = <2>;
#size-cells = <1>;
ranges;
stdout-path = &serial2;
framebuffer@67000000 {
compatible = "simple-framebuffer";
reg = <0x0 0x67000000 (720 * 1280 * 4)>;
width = <720>;
height = <1280>;
stride = <(720 * 4)>;
format = "a8r8g8b8";
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&key_power &key_voldown &key_volup>;
key-home {
interrupt-parent = <&gpa1>;
linux,code = <KEY_HOMEPAGE>;
label = "gpio-keys: KEY_HOMEPAGE";
gpios = <&gpa1 7 GPIO_ACTIVE_LOW>;
};
key-power {
interrupt-parent = <&gpa0>;
linux,code = <KEY_POWER>;
label = "gpio-keys: KEY_POWER";
gpios = <&gpa0 0 GPIO_ACTIVE_LOW>;
};
key-voldown {
interrupt-parent = <&gpa2>;
linux,code = <KEY_VOLUMEDOWN>;
label = "gpio-keys: KEY_VOLUMEDOWN";
gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
};
key-volup {
interrupt-parent = <&gpa2>;
linux,code = <KEY_VOLUMEUP>;
label = "gpio-keys: KEY_VOLUMEUP";
gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
};
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0x3e400000>,
<0x0 0x80000000 0x40000000>;
};
pwrseq_mmc1: pwrseq-mmc1 {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpd3 6 GPIO_ACTIVE_LOW>;
};
vdd_fixed_mmc2: regulator-fixed-mmc2 {
compatible = "regulator-fixed";
regulator-name = "vdd_fixed_mmc2";
regulator-max-microvolt = <2800000>;
regulator-min-microvolt = <2800000>;
gpio = <&gpc0 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <1>;
ranges;
ramoops@46e00000 {
compatible = "ramoops";
reg = <0x0 0x46e00000 0x8000>;
console-size = <0x4000>;
pmsg-size = <0x4000>;
};
framebuffer@67000000 {
reg = <0x0 0x67000000 (720 * 1280 * 4)>;
no-map;
};
};
vibrator {
compatible = "regulator-haptic";
haptic-supply = <&vdd_ldo32>;
min-microvolt = <3300000>;
max-microvolt = <3300000>;
};
};
&gpu {
status = "okay";
};
&hsi2c0 {
status = "okay";
pmic@66 {
compatible = "samsung,s2mpu05-pmic";
reg = <0x66>;
interrupt-parent = <&gpa0>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_irq>;
regulators {
vdd_buck1: buck1 {
regulator-name = "vdd_buck1";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <12000>;
regulator-boot-on;
regulator-always-on;
};
vdd_buck2: buck2 {
regulator-name = "vdd_buck2";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <12000>;
regulator-boot-on;
regulator-always-on;
};
vdd_buck3: buck3 {
regulator-name = "vdd_buck3";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <12000>;
regulator-boot-on;
regulator-always-on;
};
vdd_buck4: buck4 {
regulator-name = "vdd_buck4";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <12000>;
regulator-boot-on;
regulator-always-on;
};
vdd_buck5: buck5 {
regulator-name = "vdd_buck5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2100000>;
regulator-ramp-delay = <12000>;
regulator-boot-on;
regulator-always-on;
};
vdd_ldo1: ldo1 {
regulator-name = "vdd_ldo1";
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12000>;
regulator-boot-on;
regulator-always-on;
};
vdd_ldo2: ldo2 {
regulator-name = "vdd_ldo2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2800000>;
regulator-ramp-delay = <12000>;
};
vdd_ldo3: ldo3 {
regulator-name = "vdd_ldo3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <2375000>;
regulator-ramp-delay = <12000>;
regulator-boot-on;
regulator-always-on;
};
vdd_ldo4: ldo4 {
regulator-name = "vdd_ldo4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12000>;
regulator-boot-on;
regulator-always-on;
};
vdd_ldo5: ldo5 {
regulator-name = "vdd_ldo5";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12000>;
regulator-boot-on;
regulator-always-on;
};
vdd_ldo6: ldo6 {
regulator-name = "vdd_ldo6";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12000>;
regulator-boot-on;
regulator-always-on;
};
vdd_ldo7: ldo7 {
regulator-name = "vdd_ldo7";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <2375000>;
regulator-ramp-delay = <12000>;
regulator-boot-on;
regulator-always-on;
};
vdd_ldo8: ldo8 {
regulator-name = "vdd_ldo8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3375000>;
regulator-ramp-delay = <12000>;
};
vdd_ldo9: ldo9 {
regulator-name = "vdd_ldo9";
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12000>;
regulator-boot-on;
regulator-always-on;
};
vdd_ldo10: ldo10 {
regulator-name = "vdd_ldo10";
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12000>;
regulator-boot-on;
regulator-always-on;
};
vdd_ldo25: ldo25 {
regulator-name = "vdd_ldo25";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <2375000>;
regulator-ramp-delay = <12000>;
regulator-boot-on;
regulator-always-on;
};
vdd_ldo26: ldo26 {
regulator-name = "vdd_ldo26";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3375000>;
regulator-ramp-delay = <12000>;
regulator-boot-on;
regulator-always-on;
};
vdd_ldo27: ldo27 {
regulator-name = "vdd_ldo27";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <2375000>;
regulator-ramp-delay = <12000>;
regulator-boot-on;
regulator-always-on;
};
vdd_ldo29: ldo29 {
regulator-name = "vdd_ldo29";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vdd_ldo30: ldo30 {
regulator-name = "vdd_ldo30";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
vdd_ldo31: ldo31 {
regulator-name = "vdd_ldo31";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-ramp-delay = <12000>;
regulator-boot-on;
regulator-always-on;
};
vdd_ldo32: ldo32 {
regulator-name = "vdd_ldo32";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12000>;
};
vdd_ldo33: ldo33 {
regulator-name = "vdd_ldo33";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <12000>;
};
vdd_ldo34: ldo34 {
regulator-name = "vdd_ldo34";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdd_ldo35: ldo35 {
regulator-name = "vdd_ldo35";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c2 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <400000>;
status = "okay";
touchscreen@50 {
compatible = "imagis,ist3038h";
reg = <0x50>;
interrupt-parent = <&gpa0>;
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&touch_irq>;
touchscreen-size-x = <720>;
touchscreen-size-y = <1280>;
vdd-supply = <&vdd_ldo34>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_rdqs &sd0_bus1 &sd0_bus4 &sd0_bus8>;
vmmc-supply = <&vdd_ldo26>;
vqmmc-supply = <&vdd_ldo27>;
fifo-depth = <64>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <2 4>;
non-removable;
status = "okay";
};
&mmc1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus1 &sd1_bus4>;
mmc-pwrseq = <&pwrseq_mmc1>;
bus-width = <4>;
fifo-depth = <64>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
non-removable;
cap-sd-highspeed;
cap-sdio-irq;
status = "okay";
wifi@0 {
compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac";
reg = <0x0>;
interrupt-names = "host-wake";
interrupt-parent = <&gpa2>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpd3 6 GPIO_ACTIVE_LOW>;
};
};
&oscclk {
clock-frequency = <26000000>;
};
&pinctrl_alive {
accel_irq: accel-irq-pins {
samsung,pins = "gpa2-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
};
dwmmc2_irq: dwmmc2-irq-pins {
samsung,pins = "gpa0-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
};
fuel_irq: fuel-irq-pins {
samsung,pins = "gpa0-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
};
hall_irq: hall-irq-pins {
samsung,pins = "gpa1-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
};
key_power: key-power-pins {
samsung,pins = "gpa0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
};
key_voldown: key-voldown-pins {
samsung,pins = "gpa2-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
};
key_volup: key-volup-pins {
samsung,pins = "gpa2-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
};
pmic_irq: pmic-irq-pins {
samsung,pins = "gpa0-2";
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
};
touch_irq: touch-irq-pins {
samsung,pins = "gpa0-6";
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
};
wlan_hostwake: wlan-hostwake-pins {
samsung,pins = "gpa2-2";
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
};
};
&pinctrl_top {
wlan_enable: wlan-enable-pins {
samsung,pins = "gpd3-6";
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
samsung,pin-val = <0>;
};
};
&serial2 {
status = "okay";
};
&usbdrd {
vdd33-supply = <&vdd_ldo8>;
status = "okay";
};

6
arch/arm64/boot/dts/exynos/exynos7870-j6lte.dts
View File

@ -383,9 +383,6 @@ vdd_ldo35: ldo35 {
};
&i2c5 {
#address-cells = <1>;
#size-cells = <0>;
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <400000>;
@ -409,9 +406,6 @@ accelerometer@1d {
};
&i2c6 {
#address-cells = <1>;
#size-cells = <0>;
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <400000>;

494
arch/arm64/boot/dts/exynos/exynos7870-j7xelte.dts Normal file
View File

@ -0,0 +1,494 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Samsung Galaxy J7 (2016) (j7xelte) device tree source
*
* Copyright (c) 2025 Rayan Marzouk <rayanmarzouk743@gmail.com>
*/
/dts-v1/;
#include "exynos7870.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "Samsung Galaxy J7 (2016)";
compatible = "samsung,j7xelte", "samsung,exynos7870";
chassis-type = "handset";
aliases {
mmc0 = &mmc0;
mmc1 = &mmc1;
mmc2 = &mmc2;
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
};
chosen {
#address-cells = <2>;
#size-cells = <1>;
ranges;
stdout-path = &serial2;
framebuffer@67000000 {
compatible = "simple-framebuffer";
reg = <0x0 0x67000000 (720 * 1280 * 4)>;
width = <720>;
height = <1280>;
stride = <(720 * 4)>;
format = "a8r8g8b8";
};
};
gpio-keys {
compatible = "gpio-keys";
label = "GPIO Keys";
pinctrl-names = "default";
pinctrl-0 = <&key_home &key_power &key_voldown &key_volup>;
key-home {
label = "Home Key";
gpios = <&gpa1 7 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOMEPAGE>;
};
key-power {
label = "Power Key";
gpios = <&gpa0 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
};
key-voldown {
label = "Volume Down Key";
gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
key-volup {
label = "Volume Up Key";
gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0x3e400000>,
<0x0 0x80000000 0x40000000>;
};
pwrseq_mmc1: pwrseq-mmc1 {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpd3 6 GPIO_ACTIVE_LOW>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <1>;
ranges;
ramoops@46e00000 {
compatible = "ramoops";
reg = <0x0 0x46e00000 0x8000>;
console-size = <0x4000>;
pmsg-size = <0x4000>;
};
cont_splash_mem: framebuffer@67000000 {
reg = <0x0 0x67000000 0x00384000>;
no-map;
};
};
vdd_fixed_mmc2: regulator-fixed-mmc2 {
compatible = "regulator-fixed";
regulator-name = "vdd_fixed_mmc2";
regulator-max-microvolt = <2800000>;
regulator-min-microvolt = <2800000>;
gpio = <&gpc0 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vibrator {
compatible = "regulator-haptic";
haptic-supply = <&vdd_ldo32>;
min-microvolt = <3300000>;
max-microvolt = <3300000>;
};
};
&gpu {
status = "okay";
};
&hsi2c0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pmic@66 {
compatible = "samsung,s2mpu05-pmic";
reg = <0x66>;
interrupt-parent = <&gpa0>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_irq>;
regulators {
vdd_buck1: buck1 {
regulator-name = "vdd_buck1";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
regulator-boot-on;
};
vdd_buck2: buck2 {
regulator-name = "vdd_buck2";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
regulator-boot-on;
};
vdd_buck3: buck3 {
regulator-name = "vdd_buck3";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
regulator-boot-on;
};
vdd_buck4: buck4 {
regulator-name = "vdd_buck4";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
};
vdd_buck5: buck5 {
regulator-name = "vdd_buck5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2100000>;
regulator-always-on;
regulator-boot-on;
};
vdd_ldo1: ldo1 {
regulator-name = "vdd_ldo1";
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
};
vdd_ldo2: ldo2 {
regulator-name = "vdd_ldo2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2800000>;
};
vdd_ldo3: ldo3 {
regulator-name = "vdd_ldo3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <2375000>;
regulator-always-on;
regulator-boot-on;
};
vdd_ldo4: ldo4 {
regulator-name = "vdd_ldo4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
};
vdd_ldo5: ldo5 {
regulator-name = "vdd_ldo5";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
};
vdd_ldo6: ldo6 {
regulator-name = "vdd_ldo6";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
};
vdd_ldo7: ldo7 {
regulator-name = "vdd_ldo7";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <2375000>;
regulator-always-on;
regulator-boot-on;
};
vdd_ldo8: ldo8 {
regulator-name = "vdd_ldo8";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdd_ldo9: ldo9 {
regulator-name = "vdd_ldo9";
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
};
vdd_ldo10: ldo10 {
regulator-name = "vdd_ldo10";
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
};
vdd_ldo25: ldo25 {
regulator-name = "vdd_ldo25";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <2375000>;
regulator-always-on;
regulator-boot-on;
};
vdd_ldo26: ldo26 {
regulator-name = "vdd_ldo26";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3375000>;
};
vdd_ldo27: ldo27 {
regulator-name = "vdd_ldo27";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <2375000>;
};
vdd_ldo29: ldo29 {
regulator-name = "vdd_ldo29";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-boot-on;
};
vdd_ldo30: ldo30 {
regulator-name = "vdd_ldo30";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
vdd_ldo31: ldo31 {
regulator-name = "vdd_ldo31";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
regulator-boot-on;
};
vdd_ldo32: ldo32 {
regulator-name = "vdd_ldo32";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vdd_ldo33: ldo33 {
regulator-name = "vdd_ldo33";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vdd_ldo34: ldo34 {
regulator-name = "vdd_ldo34";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vdd_ldo35: ldo35 {
regulator-name = "vdd_ldo35";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
regulator-boot-on;
};
};
};
};
&i2c1 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <400000>;
status = "okay";
touchscreen@48 {
compatible = "melfas,mip4_ts";
reg = <0x48>;
interrupt-parent = <&gpc3>;
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&touch_irq>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_rdqs &sd0_bus1 &sd0_bus4 &sd0_bus8>;
vmmc-supply = <&vdd_ldo26>;
vqmmc-supply = <&vdd_ldo27>;
fifo-depth = <64>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <2 4>;
non-removable;
status = "okay";
};
&mmc1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus1 &sd1_bus4>;
mmc-pwrseq = <&pwrseq_mmc1>;
bus-width = <4>;
fifo-depth = <64>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
non-removable;
cap-sd-highspeed;
cap-sdio-irq;
status = "okay";
wifi@1 {
compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac";
reg = <0x1>;
interrupt-names = "host-wake";
interrupt-parent = <&gpa2>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpd3 6 GPIO_ACTIVE_LOW>;
};
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4 &dwmmc2_irq>;
vmmc-supply = <&vdd_fixed_mmc2>;
vqmmc-supply = <&vdd_ldo2>;
bus-width = <4>;
card-detect-delay = <200>;
fifo-depth = <64>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
sd-uhs-sdr50;
sd-uhs-sdr104;
broken-cd;
disable-wp;
status = "okay";
};
&oscclk {
clock-frequency = <26000000>;
};
&pinctrl_alive {
dwmmc2_irq: dwmmc2-irq-pins {
samsung,pins = "gpa0-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
};
fuel_irq: fuel-irq-pins {
samsung,pins = "gpa0-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
};
key_home: key-home-pins {
samsung,pins = "gpa1-7";
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
};
key_power: key-power-pins {
samsung,pins = "gpa0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
};
key_voldown: key-voldown-pins {
samsung,pins = "gpa2-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
};
key_volup: key-volup-pins {
samsung,pins = "gpa2-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
};
pmic_irq: pmic-irq-pins {
samsung,pins = "gpa0-2";
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR3>;
};
};
&pinctrl_touch {
touch_irq: touch-irq-pins {
samsung,pins = "gpc3-2";
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
};
};
&serial2 {
status = "okay";
};
&usbdrd {
vdd33-supply = <&vdd_ldo8>;
status = "okay";
};

9
arch/arm64/boot/dts/exynos/exynos7870-on7xelte.dts
View File

@ -398,9 +398,6 @@ vdd_ldo35: ldo35 {
};
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <400000>;
@ -438,9 +435,6 @@ rmi4-f12@12 {
};
&i2c7 {
#address-cells = <1>;
#size-cells = <0>;
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <400000>;
@ -464,9 +458,6 @@ accelerometer@1d {
};
&i2c8 {
#address-cells = <1>;
#size-cells = <0>;
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <400000>;

48
arch/arm64/boot/dts/exynos/exynos7870.dtsi
View File

@ -220,6 +220,9 @@ hsi2c0: i2c@10510000 {
clock-names = "hsi2c";
clocks = <&cmu_mif CLK_GOUT_MIF_HSI2C_IPCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -422,6 +425,9 @@ i2c0: i2c@13830000 {
clock-names = "i2c";
clocks = <&cmu_peri CLK_GOUT_PERI_I2C0_PCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -437,6 +443,9 @@ i2c1: i2c@13840000 {
clock-names = "i2c";
clocks = <&cmu_peri CLK_GOUT_PERI_I2C1_PCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -452,6 +461,9 @@ i2c2: i2c@13850000 {
clock-names = "i2c";
clocks = <&cmu_peri CLK_GOUT_PERI_I2C2_PCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -467,6 +479,9 @@ i2c3: i2c@13860000 {
clock-names = "i2c";
clocks = <&cmu_peri CLK_GOUT_PERI_I2C3_PCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -482,6 +497,9 @@ i2c4: i2c@13870000 {
clock-names = "i2c";
clocks = <&cmu_peri CLK_GOUT_PERI_I2C4_PCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -497,6 +515,9 @@ i2c5: i2c@13880000 {
clock-names = "i2c";
clocks = <&cmu_peri CLK_GOUT_PERI_I2C5_PCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -512,6 +533,9 @@ i2c6: i2c@13890000 {
clock-names = "i2c";
clocks = <&cmu_peri CLK_GOUT_PERI_I2C6_PCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -527,6 +551,9 @@ hsi2c1: i2c@138a0000 {
clock-names = "hsi2c";
clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C1_IPCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -542,6 +569,9 @@ hsi2c2: i2c@138b0000 {
clock-names = "hsi2c";
clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C2_IPCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -557,6 +587,9 @@ hsi2c3: i2c@138c0000 {
clock-names = "hsi2c";
clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C3_IPCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -572,6 +605,9 @@ i2c7: i2c@138d0000 {
clock-names = "i2c";
clocks = <&cmu_peri CLK_GOUT_PERI_I2C7_PCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -587,6 +623,9 @@ i2c8: i2c@138e0000 {
clock-names = "i2c";
clocks = <&cmu_peri CLK_GOUT_PERI_I2C8_PCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -602,6 +641,9 @@ hsi2c4: i2c@138f0000 {
clock-names = "hsi2c";
clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C4_IPCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -617,6 +659,9 @@ hsi2c5: i2c@13950000 {
clock-names = "hsi2c";
clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C5_IPCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -632,6 +677,9 @@ hsi2c6: i2c@13960000 {
clock-names = "hsi2c";
clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C6_IPCLK>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};

2
arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts
View File

@ -103,8 +103,6 @@ reg_placeholder: regulator-0 {
};
&hsi2c_23 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
touchscreen@48 {

128
arch/arm64/boot/dts/exynos/exynos8895.dtsi
View File

@ -266,6 +266,10 @@ hsi2c_5: i2c@0 {
interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c5_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -305,6 +309,10 @@ hsi2c_6: i2c@10000 {
interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c6_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
@ -328,6 +336,10 @@ hsi2c_7: i2c@0 {
interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c5_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -367,6 +379,10 @@ hsi2c_8: i2c@10000 {
interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c8_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
@ -390,6 +406,10 @@ hsi2c_9: i2c@0 {
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c9_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -429,6 +449,10 @@ hsi2c_10: i2c@10000 {
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c10_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
@ -452,6 +476,10 @@ hsi2c_11: i2c@0 {
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c11_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -491,6 +519,10 @@ hsi2c_12: i2c@10000 {
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c12_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
@ -565,6 +597,10 @@ hsi2c_13: i2c@0 {
interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c13_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -604,6 +640,10 @@ hsi2c_14: i2c@10000 {
interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c14_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
@ -627,6 +667,10 @@ hsi2c_15: i2c@0 {
interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c15_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -666,6 +710,10 @@ hsi2c_16: i2c@10000 {
interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c16_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
@ -689,6 +737,10 @@ hsi2c_17: i2c@0 {
interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c17_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -728,6 +780,10 @@ hsi2c_18: i2c@10000 {
interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c18_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
@ -751,6 +807,10 @@ hsi2c_19: i2c@0 {
interrupts = <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c19_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -790,6 +850,10 @@ hsi2c_20: i2c@10000 {
interrupts = <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c20_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
@ -813,6 +877,10 @@ hsi2c_21: i2c@0 {
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c21_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -852,6 +920,10 @@ hsi2c_22: i2c@10000 {
interrupts = <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c22_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
@ -875,6 +947,10 @@ hsi2c_23: i2c@0 {
interrupts = <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c23_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -914,6 +990,10 @@ hsi2c_24: i2c@10000 {
interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c24_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
@ -937,6 +1017,10 @@ hsi2c_25: i2c@0 {
interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c25_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -976,6 +1060,10 @@ hsi2c_26: i2c@10000 {
interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c26_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
@ -999,6 +1087,10 @@ hsi2c_27: i2c@0 {
interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c27_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -1038,6 +1130,10 @@ hsi2c_28: i2c@10000 {
interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c28_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
@ -1061,6 +1157,10 @@ hsi2c_29: i2c@0 {
interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c29_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -1100,6 +1200,10 @@ hsi2c_30: i2c@10000 {
interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c30_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
@ -1123,6 +1227,10 @@ hsi2c_31: i2c@0 {
interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c31_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -1162,6 +1270,10 @@ hsi2c_32: i2c@10000 {
interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c32_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
@ -1180,6 +1292,10 @@ hsi2c_1: i2c@10990000 {
interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c1_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -1191,6 +1307,10 @@ hsi2c_2: i2c@109a0000 {
interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c2_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -1202,6 +1322,10 @@ hsi2c_3: i2c@109b0000 {
interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c3_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -1213,6 +1337,10 @@ hsi2c_4: i2c@109c0000 {
interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&hsi2c4_bus>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};

13
arch/arm64/boot/dts/exynos/exynosautov920.dtsi
View File

@ -1473,6 +1473,19 @@ cmu_mfd: clock-controller@19e00000 {
"noc";
};
cmu_g3d: clock-controller@1a000000 {
compatible = "samsung,exynosautov920-cmu-g3d";
reg = <0x1a000000 0x8000>;
#clock-cells = <1>;
clocks = <&xtcxo>,
<&cmu_top DOUT_CLKCMU_G3D_SWITCH>,
<&cmu_top DOUT_CLKCMU_G3D_NOCP>;
clock-names = "oscclk",
"switch",
"nocp";
};
pinctrl_aud: pinctrl@1a460000 {
compatible = "samsung,exynosautov920-pinctrl";
reg = <0x1a460000 0x10000>;

22
arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
View File

@ -8,6 +8,7 @@
/dts-v1/;
#include <dt-bindings/regulator/samsung,s2mpg10-regulator.h>
#include "gs101-pixel-common.dtsi"
/ {
@ -15,6 +16,27 @@ / {
compatible = "google,gs101-oriole", "google,gs101";
};
&acpm_ipc {
pmic-1 {
regulators {
ldo14m {
/* PLL */
regulator-name = "avdd18_tcxo";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1950000>;
regulator-always-on;
samsung,ext-control = <S2MPG10_EXTCTRL_TCXO_ON>;
};
ldo31m {
regulator-name = "nfc";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1950000>;
};
};
};
};
&cont_splash_mem {
reg = <0x0 0xfac00000 (1080 * 2400 * 4)>;
status = "okay";

528
arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi
View File

@ -10,6 +10,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/regulator/samsung,s2mpg10-regulator.h>
#include <dt-bindings/usb/pd.h>
#include "gs101-pinctrl.h"
#include "gs101.dtsi"
@ -28,6 +29,8 @@ chosen {
framebuffer0: framebuffer-0 {
compatible = "simple-framebuffer";
memory-region = <&cont_splash_mem>;
vci-supply = <&s2mpg10_ldo22m>;
vddi-supply = <&s2mpg11_bucka>;
/* format properties to be added by actual board */
status = "disabled";
};
@ -101,7 +104,7 @@ cont_splash_mem: splash@fac00000 {
};
&acpm_ipc {
pmic {
pmic-1 {
compatible = "samsung,s2mpg10-pmic";
interrupts-extended = <&gpa0 6 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
@ -109,6 +112,22 @@ pmic {
system-power-controller;
wakeup-source;
vinl1m-supply = <&s2mpg11_buck3s>;
vinl2m-supply = <&s2mpg11_buck3s>;
vinl3m-supply = <&s2mpg10_buck8m>;
vinl4m-supply = <&s2mpg10_buck9m>;
vinl5m-supply = <&s2mpg10_buck9m>;
vinl6m-supply = <&s2mpg10_buck9m>;
vinl7m-supply = <&s2mpg11_buck6s>;
vinl8m-supply = <&s2mpg11_buck6s>;
vinl9m-supply = <&s2mpg11_buck7s>;
vinl10m-supply = <&s2mpg11_buck7s>;
vinl11m-supply = <&s2mpg11_buck7s>;
vinl12m-supply = <&s2mpg11_bucka>;
vinl13m-supply = <&s2mpg11_bucka>;
vinl14m-supply = <&s2mpg11_buckboost>;
vinl15m-supply = <&s2mpg11_buckboost>;
clocks {
compatible = "samsung,s2mpg10-clk";
#clock-cells = <1>;
@ -117,6 +136,489 @@ clocks {
};
regulators {
buck1m {
regulator-name = "vdd_mif";
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <6250>;
regulator-always-on;
samsung,ext-control = <S2MPG10_EXTCTRL_PWREN_MIF>;
};
buck2m {
regulator-name = "vdd_cpucl2";
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
samsung,ext-control = <S2MPG10_EXTCTRL_CPUCL2_EN2>;
};
buck3m {
regulator-name = "vdd_cpucl1";
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
samsung,ext-control = <S2MPG10_EXTCTRL_CPUCL1_EN2>;
};
buck4m {
regulator-name = "vdd_cpucl0";
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
samsung,ext-control = <S2MPG10_EXTCTRL_PWREN>;
};
buck5m {
regulator-name = "vdd_int";
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
samsung,ext-control = <S2MPG10_EXTCTRL_PWREN_MIF>;
};
buck6m {
regulator-name = "vdd_cpucl2_m";
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
samsung,ext-control = <S2MPG10_EXTCTRL_CPUCL2_EN2>;
};
buck7m {
/* GPU */
regulator-name = "vdd_int_m";
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <6250>;
regulator-always-on;
samsung,ext-control = <S2MPG10_EXTCTRL_PWREN_MIF>;
};
s2mpg10_buck8m: buck8m {
regulator-name = "lldo2";
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <6250>;
};
s2mpg10_buck9m: buck9m {
regulator-name = "lldo3";
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <6250>;
};
buck10m {
regulator-name = "vdd_tpu";
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
samsung,ext-control = <S2MPG10_EXTCTRL_TPU_EN>;
};
ldo1m {
/* ALIVE, AOC PLL */
regulator-name = "vdd_l1m_alive";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <6250>;
regulator-always-on;
};
ldo2m {
/* lots, DDR */
regulator-name = "vdd_l2m_alive";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1950000>;
regulator-always-on;
};
ldo3m {
/* AVDD: MIPI CSI & DSI, PLL: CPUCL SHARED TPU UFS */
regulator-name = "ldo3m";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
samsung,ext-control = <S2MPG10_EXTCTRL_PWREN_MIF>;
};
ldo4m {
/* AVDD: MIPI CSI & DSI, UFS, OTP, TS_SUB, TS_TOP, XOTP */
regulator-name = "ldo4m";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1950000>;
regulator-always-on;
samsung,ext-control = <S2MPG10_EXTCTRL_PWREN_MIF>;
};
ldo5m {
/* VDD: ADD, AVDD: TCXO & TCXO_FAR */
regulator-name = "avdd075_tcxo";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
samsung,ext-control = <S2MPG10_EXTCTRL_TCXO_ON>;
};
ldo6m {
/* PLL CPUCL & MIFx, UFS clk, MIPI DSI */
regulator-name = "vdd_pll";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
samsung,ext-control = <S2MPG10_EXTCTRL_PWREN_MIF>;
};
ldo7m {
/* IO (HSI (USB)) */
regulator-name = "vdd_hsi";
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <6250>;
/*
* TODO: link to HSI power domain, without this,
* Linux hangs during USB access.
*/
regulator-always-on;
};
ldo8m {
regulator-name = "vdd085_usb";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
};
ldo9m {
regulator-name = "vdd18_usb";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1950000>;
regulator-always-on;
};
ldo10m {
regulator-name = "vdd33_usb";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3350000>;
regulator-always-on;
};
ldo11m {
regulator-name = "vdd_cpucl1_m";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <6250>;
regulator-always-on;
samsung,ext-control = <S2MPG10_EXTCTRL_CPUCL1_EN2>;
};
ldo12m {
regulator-name = "vdd_cpucl0_m";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <6250>;
regulator-always-on;
samsung,ext-control = <S2MPG10_EXTCTRL_PWREN>;
};
ldo13m {
regulator-name = "vdd_tpu_m";
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
samsung,ext-control = <S2MPG10_EXTCTRL_TPU_EN>;
};
/* ldo14m is board specific */
ldo15m {
regulator-name = "vdd_slc_m";
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
};
ldo16m {
regulator-name = "vdd085_pcie0";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1300000>;
};
ldo17m {
regulator-name = "vdd085_pcie1";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1300000>;
};
ldo18m {
regulator-name = "vdd18_pcie0";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1950000>;
};
ldo19m {
regulator-name = "vdd18_pcie1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1950000>;
};
ldo20m {
/* DMIC, memory power */
regulator-name = "vddq_aoc_pdm";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1950000>;
regulator-always-on;
samsung,ext-control = <S2MPG10_EXTCTRL_LDO20M_EN2>;
};
ldo21m {
/* Dauntless */
regulator-name = "vdd_dtls";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
s2mpg10_ldo22m: ldo22m {
/* display */
regulator-name = "vci_disp";
regulator-min-microvolt = <3025000>;
regulator-max-microvolt = <3025000>;
};
/* ldo23m & ldo24m are unused */
ldo25m {
/* touch */
regulator-name = "dvdd_tsp";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1950000>;
};
ldo26m {
/* touch */
regulator-name = "avdd_ts";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3300000>;
};
ldo27m {
/* under-display fingerprint scanner */
regulator-name = "avdd_udfps";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3300000>;
};
/*
*ldo28m .. ldo30m are unused, ldo31m is board specific
*/
};
};
pmic-2 {
compatible = "samsung,s2mpg11-pmic";
interrupts-extended = <&gpa0 7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sub_pmic_int>;
wakeup-source;
vinl1s-supply = <&s2mpg10_buck8m>;
vinl2s-supply = <&s2mpg11_buck6s>;
vinl3s-supply = <&s2mpg11_buck7s>;
vinl4s-supply = <&s2mpg11_buck7s>;
vinl5s-supply = <&s2mpg11_buckboost>;
vinl6s-supply = <&s2mpg11_buckboost>;
vinbd-supply = <&s2mpg11_buckboost>;
regulators {
buck1s {
/* multimedia */
regulator-name = "vdd_cam";
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
samsung,ext-control = <S2MPG11_EXTCTRL_PWREN_MIF>;
};
buck2s {
regulator-name = "vdd_g3d";
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
samsung,ext-control = <S2MPG11_EXTCTRL_G3D_EN>;
};
s2mpg11_buck3s: buck3s {
regulator-name = "lldo1";
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <6250>;
};
buck4s {
/* DDR */
regulator-name = "vdd2h_mem";
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <6250>;
regulator-always-on;
};
buck5s {
/* DDR */
regulator-name = "vddq_mem";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <6250>;
regulator-always-on;
samsung,ext-control = <S2MPG11_EXTCTRL_PWREN_MIF>;
};
s2mpg11_buck6s: buck6s {
regulator-name = "lldo4";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <6250>;
};
s2mpg11_buck7s: buck7s {
regulator-name = "mldo";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2200000>;
regulator-ramp-delay = <6250>;
};
buck8s {
regulator-name = "vdd_g3d_l2";
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
samsung,ext-control = <S2MPG11_EXTCTRL_G3D_EN>;
};
buck9s {
regulator-name = "vdd_aoc";
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
};
buck10s {
/* DDR */
regulator-name = "vdd2l_mem";
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <1300000>;
regulator-ramp-delay = <6250>;
regulator-always-on;
};
buckd {
regulator-name = "vcc_ufs";
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <6250>;
regulator-always-on;
samsung,ext-control = <S2MPG11_EXTCTRL_UFS_EN>;
};
s2mpg11_bucka: bucka {
/* lots, IO */
regulator-name = "bucka";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <2100000>;
regulator-ramp-delay = <6250>;
regulator-always-on;
};
s2mpg11_buckboost: buckboost {
regulator-name = "buckboost";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3600000>;
};
ldo1s {
regulator-name = "vdd_g3d_m";
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <6250>;
regulator-always-on;
samsung,ext-control = <S2MPG11_EXTCTRL_G3D_EN>;
};
ldo2s {
regulator-name = "vdd_aoc_ret";
regulator-min-microvolt = <450000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
};
/* ldo3s & ldo5s are unused, ldo4s is board specific */
ldo6s {
/* sensors */
regulator-name = "vdd_prox";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3300000>;
};
ldo7s {
/* sensors */
regulator-name = "vdd_sensors";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1950000>;
};
ldo8s {
regulator-name = "vccq_ufs";
regulator-min-microvolt = <1130400>;
regulator-max-microvolt = <1281200>;
regulator-always-on;
samsung,ext-control = <S2MPG11_EXTCTRL_UFS_EN>;
};
ldo9s {
regulator-name = "vdd_gnss";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1300000>;
};
ldo10s {
regulator-name = "vdd_gnss_rf";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1950000>;
};
ldo11s {
regulator-name = "vdd_gnss_aux";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1950000>;
};
/* ldo12s is unused */
ldo13s {
regulator-name = "vddq_mmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3350000>;
regulator-always-on;
samsung,ext-control = <S2MPG11_EXTCTRL_LDO13S_EN>;
};
/* ldo14s is board specific, ldo15s is unused */
};
};
};
@ -225,6 +727,17 @@ usbc0_role_sw: endpoint {
};
};
fuel-gauge@36 {
compatible = "maxim,max77759-fg";
reg = <0x36>;
pinctrl-0 = <&if_pmic_fg_int>;
pinctrl-names = "default";
interrupts-extended = <&gpa9 3 IRQ_TYPE_LEVEL_LOW>;
shunt-resistor-micro-ohms = <5000>;
};
pmic@66 {
compatible = "maxim,max77759";
reg = <0x66>;
@ -317,6 +830,19 @@ pmic_int: pmic-int-pins {
samsung,pin-pud = <GS101_PIN_PULL_NONE>;
};
sub_pmic_int: sub-pmic-int-pins {
samsung,pins = "gpa0-7";
samsung,pin-function = <GS101_PIN_FUNC_EINT>;
samsung,pin-pud = <GS101_PIN_PULL_NONE>;
};
if_pmic_fg_int: if-pmic-fg-int-pins {
samsung,pins = "gpa9-3";
samsung,pin-function = <GS101_PIN_FUNC_EINT>;
samsung,pin-pud = <GS101_PIN_PULL_UP>;
samsung,pin-drv = <GS101_PIN_DRV_2_5_MA>;
};
key_power: key-power-pins {
samsung,pins = "gpa10-1";
samsung,pin-function = <GS101_PIN_FUNC_EINT>;

18
arch/arm64/boot/dts/exynos/google/gs101-raven.dts
View File

@ -15,6 +15,24 @@ / {
compatible = "google,gs101-raven", "google,gs101";
};
&acpm_ipc {
pmic-2 {
regulators {
ldo4s {
regulator-name = "vdd2_uwb";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3300000>;
};
ldo14s {
regulator-name = "vdd3_uwb";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1950000>;
};
};
};
};
&cont_splash_mem {
reg = <0x0 0xfac00000 (1440 * 3120 * 4)>;
status = "okay";

195
include/dt-bindings/clock/axis,artpec9-clk.h Normal file
View File

@ -0,0 +1,195 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2025 Samsung Electronics Co., Ltd.
* https://www.samsung.com
* Copyright (c) 2025 Axis Communications AB.
* https://www.axis.com
*
* Device Tree binding constants for ARTPEC-9 clock controller.
*/
#ifndef _DT_BINDINGS_CLOCK_ARTPEC9_H
#define _DT_BINDINGS_CLOCK_ARTPEC9_H
/* CMU_CMU */
#define CLK_FOUT_SHARED0_PLL 1
#define CLK_DOUT_SHARED0_DIV2 2
#define CLK_DOUT_SHARED0_DIV3 3
#define CLK_DOUT_SHARED0_DIV4 4
#define CLK_FOUT_SHARED1_PLL 5
#define CLK_DOUT_SHARED1_DIV2 6
#define CLK_DOUT_SHARED1_DIV3 7
#define CLK_DOUT_SHARED1_DIV4 8
#define CLK_FOUT_AUDIO_PLL 9
#define CLK_DOUT_CMU_ADD 10
#define CLK_DOUT_CMU_BUS 11
#define CLK_DOUT_CMU_CDC_CORE 12
#define CLK_DOUT_CMU_CORE_MAIN 13
#define CLK_DOUT_CMU_CPUCL_SWITCH 14
#define CLK_DOUT_CMU_DLP_CORE 15
#define CLK_DOUT_CMU_FSYS0_BUS 16
#define CLK_DOUT_CMU_FSYS0_IP 17
#define CLK_DOUT_CMU_FSYS1_BUS 18
#define CLK_DOUT_CMU_FSYS1_SCAN0 19
#define CLK_DOUT_CMU_FSYS1_SCAN1 20
#define CLK_DOUT_CMU_GPU_3D 21
#define CLK_DOUT_CMU_GPU_2D 22
#define CLK_DOUT_CMU_IMEM_ACLK 23
#define CLK_DOUT_CMU_IMEM_CA5 24
#define CLK_DOUT_CMU_IMEM_JPEG 25
#define CLK_DOUT_CMU_IMEM_SSS 26
#define CLK_DOUT_CMU_IPA_CORE 27
#define CLK_DOUT_CMU_LCPU 28
#define CLK_DOUT_CMU_MIF_SWITCH 29
#define CLK_DOUT_CMU_MIF_BUSP 30
#define CLK_DOUT_CMU_PERI_DISP 31
#define CLK_DOUT_CMU_PERI_IP 32
#define CLK_DOUT_CMU_RSP_CORE 33
#define CLK_DOUT_CMU_TRFM 34
#define CLK_DOUT_CMU_VIO_CORE_L 35
#define CLK_DOUT_CMU_VIO_CORE 36
#define CLK_DOUT_CMU_VIP0 37
#define CLK_DOUT_CMU_VIP1 38
#define CLK_DOUT_CMU_VPP_CORE 39
#define CLK_DOUT_CMU_VIO_AUDIO 40
/* CMU_BUS */
#define CLK_MOUT_BUS_ACLK_USER 1
/* CMU_CORE */
#define CLK_MOUT_CORE_ACLK_USER 1
/* CMU_CPUCL */
#define CLK_FOUT_CPUCL_PLL0 1
#define CLK_MOUT_CPUCL_PLL0 2
#define CLK_FOUT_CPUCL_PLL1 3
#define CLK_MOUT_CPUCL_PLL_SCU 4
#define CLK_MOUT_CPUCL_SWITCH_SCU_USER 5
#define CLK_MOUT_CPUCL_SWITCH_USER 6
#define CLK_DOUT_CPUCL_CPU 7
#define CLK_DOUT_CPUCL_CLUSTER_PERIPHCLK 8
#define CLK_DOUT_CPUCL_CLUSTER_GICCLK 9
#define CLK_DOUT_CPUCL_CLUSTER_PCLK 10
#define CLK_DOUT_CPUCL_CMUREF 11
#define CLK_DOUT_CPUCL_CLUSTER_ATCLK 12
#define CLK_DOUT_CPUCL_CLUSTER_SCU 13
#define CLK_DOUT_CPUCL_DBG 14
#define CLK_GOUT_CPUCL_SHORTSTOP 15
#define CLK_GOUT_CPUCL_CLUSTER_CPU 16
#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK 17
#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG 18
/* CMU_FSYS0 */
#define CLK_MOUT_FSYS0_BUS_USER 1
#define CLK_MOUT_FSYS0_IP_USER 2
#define CLK_MOUT_FSYS0_MAIN_USER 3
#define CLK_DOUT_FSYS0_125 4
#define CLK_DOUT_FSYS0_ADC 5
#define CLK_DOUT_FSYS0_BUS_300 6
#define CLK_DOUT_FSYS0_EQOS0 7
#define CLK_DOUT_FSYS0_EQOS1 8
#define CLK_DOUT_FSYS0_MMC_CARD0 9
#define CLK_DOUT_FSYS0_MMC_CARD1 10
#define CLK_DOUT_FSYS0_MMC_CARD2 11
#define CLK_DOUT_FSYS0_QSPI 12
#define CLK_DOUT_FSYS0_SFMC_NAND 13
#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 14
#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_CSR_I 15
#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_I_RGMII_PHASE_CLK_250 16
#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_I_RGMII_TXCLK 17
#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_I_RGMII_PHASE_CLK_250 18
#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_I_RGMII_TXCLK 19
#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_ACLK_I 20
#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_CLK_CSR_I 21
#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_APB_S_PCLK 22
#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_CORE_CLK 23
#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_DMA_CLK 24
#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_HDR_TX_CLK 25
#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_APB_S_PCLK 26
#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_CORE_CLK 27
#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_DMA_CLK 28
#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_HDR_TX_CLK 29
#define CLK_GOUT_FSYS0_MMC0_IPCLKPORT_SDCLKIN 30
#define CLK_GOUT_FSYS0_MMC1_IPCLKPORT_SDCLKIN 31
#define CLK_GOUT_FSYS0_MMC2_IPCLKPORT_SDCLKIN 32
#define CLK_GOUT_FSYS0_QSPI_IPCLKPORT_HCLK 33
#define CLK_GOUT_FSYS0_QSPI_IPCLKPORT_SSI_CLK 34
#define CLK_GOUT_FSYS0_SFMC_IPCLKPORT_I_ACLK_NAND 35
#define CLK_GOUT_FSYS0_I2C0_IPCLKPORT_I_PCLK 36
#define CLK_GOUT_FSYS0_I2C1_IPCLKPORT_I_PCLK 37
#define CLK_GOUT_FSYS0_MMC0_IPCLKPORT_I_ACLK 38
#define CLK_GOUT_FSYS0_MMC1_IPCLKPORT_I_ACLK 39
#define CLK_GOUT_FSYS0_MMC2_IPCLKPORT_I_ACLK 40
#define CLK_GOUT_FSYS0_PWM_IPCLKPORT_I_PCLK_S0 41
/* CMU_FSYS1 */
#define CLK_FOUT_FSYS1_PLL 1
#define CLK_MOUT_FSYS1_SCAN0_USER 2
#define CLK_MOUT_FSYS1_SCAN1_USER 3
#define CLK_MOUT_FSYS1_BUS_USER 4
#define CLK_DOUT_FSYS1_200 5
#define CLK_DOUT_FSYS1_BUS_300 6
#define CLK_DOUT_FSYS1_OTP_MEM 7
#define CLK_DOUT_FSYS1_PCIE_PHY_REFCLK_SYSPLL 8
#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_100 9
#define CLK_GOUT_FSYS1_UART0_PCLK 10
#define CLK_GOUT_FSYS1_UART0_SCLK_UART 11
#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_300 12
#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_DBI_ACLK_SOC 13
#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_MSTR_ACLK_SOC 14
#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_SLV_ACLK_SOC 15
#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_DBI_ACLK_SOC 16
#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_MSTR_ACLK_SOC 17
#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_SLV_ACLK_SOC 18
#define CLK_GOUT_FSYS1_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20 19
#define CLK_GOUT_FSYS1_USB20DRD_IPCLKPORT_BUS_CLK_EARLY 20
#define CLK_GOUT_FSYS1_XHB_AHBBR_FSYS1_IPCLKPORT_CLK 21
#define CLK_GOUT_FSYS1_XHB_USB_IPCLKPORT_CLK 22
/* CMU_IMEM */
#define CLK_MOUT_IMEM_ACLK_USER 1
#define CLK_MOUT_IMEM_CA5_USER 2
#define CLK_MOUT_IMEM_SSS_USER 3
#define CLK_MOUT_IMEM_JPEG_USER 4
#define CLK_DOUT_IMEM_PCLK 5
#define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_ATCLK 6
#define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_CLKIN 7
#define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_PCLK_DBG 8
#define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_ATCLK 9
#define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_CLKIN 10
#define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_PCLK_DBG 11
#define CLK_GOUT_IMEM_MCT0_PCLK 12
#define CLK_GOUT_IMEM_MCT1_PCLK 13
#define CLK_GOUT_IMEM_MCT2_PCLK 14
#define CLK_GOUT_IMEM_MCT3_PCLK 15
#define CLK_GOUT_IMEM_PCLK_TMU0_APBIF 16
/* CMU_PERI */
#define CLK_MOUT_PERI_IP_USER 1
#define CLK_MOUT_PERI_DISP_USER 2
#define CLK_DOUT_PERI_125 3
#define CLK_DOUT_PERI_PCLK 4
#define CLK_DOUT_PERI_SPI 5
#define CLK_DOUT_PERI_UART1 6
#define CLK_DOUT_PERI_UART2 7
#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_APB_CLK 8
#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK 9
#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_APB_S_PCLK 10
#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_CORE_CLK 11
#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_DMA_CLK 12
#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_HDR_TX_CLK 13
#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_APB_S_PCLK 14
#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_CORE_CLK 15
#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_DMA_CLK 16
#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_HDR_TX_CLK 17
#define CLK_GOUT_PERI_APB_ASYNC_DSIM_IPCLKPORT_PCLKS 18
#define CLK_GOUT_PERI_I2C2_IPCLKPORT_I_PCLK 19
#define CLK_GOUT_PERI_I2C3_IPCLKPORT_I_PCLK 20
#define CLK_GOUT_PERI_SPI0_PCLK 21
#define CLK_GOUT_PERI_SPI0_SCLK_SPI 22
#define CLK_GOUT_PERI_UART1_PCLK 23
#define CLK_GOUT_PERI_UART1_SCLK_UART 24
#define CLK_GOUT_PERI_UART2_PCLK 25
#define CLK_GOUT_PERI_UART2_SCLK_UART 26
#endif /* _DT_BINDINGS_CLOCK_ARTPEC9_H */