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platform/x86/amd/pmf: Add 1AH_M80H device IDs and extended SMU mailbox registers

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Add PCI device ID (0x115b) and ACPI ID (AMDI0109) to enable PMF driver
support for the AMD 1AH_M80H (Family 1AH Model 80H).

The 1AH_M80H platform introduces an extended SMU mailbox interface that
uses three argument registers instead of the single register used by
earlier platforms. Define five new register offsets for the 1AH_M80H
mailbox: message, response and three argument registers. The extended
argument registers are required because 1AH_M80H exposes metrics through
a firmware managed DRAM region. The GET_METRICS_TABLE_DRAM_ADDR command
returns a 64-bit physical address split across arg_reg[0] (low 32-bit)
and arg_reg[1] (high 32-bit), with the metrics table size in arg_reg[2].

Define amd_pmf_smu_regs_v2 to capture this extended register layout and
register it in pmf_pci_ids[] via PCI_DEVICE_DATA(), keeping the existing
amd_pmf_smu_regs_v1 shared instance for all prior platforms unchanged.

Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>
Co-developed-by: Patil Rajesh Reddy <Patil.Reddy@amd.com>
Signed-off-by: Patil Rajesh Reddy <Patil.Reddy@amd.com>
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Link: https://patch.msgid.link/20260723111534.1940925-3-Shyam-sundar.S-k@amd.com
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
This commit is contained in:
Shyam Sundar S K 2026-07-23 16:45:29 +05:30 committed by Ilpo Järvinen
parent e860e56192
commit 2f9db5881f
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GPG Key ID: 59AC4F6153E5CE31
2 changed files with 26 additions and 5 deletions
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28
drivers/platform/x86/amd/pmf/core.c
View File

@ -26,6 +26,13 @@
#define AMD_PMF_REGISTER_RESPONSE 0xA78
#define AMD_PMF_REGISTER_ARGUMENT 0xA58
/* PMF-SMU communication registers for 1AH_M80H */
#define AMD_PMF_REGISTER_MESSAGE_V2 0xA04
#define AMD_PMF_REGISTER_RESPONSE_V2 0xA08
#define AMD_PMF_REGISTER_ARGUMENT0_V2 0xA0C
#define AMD_PMF_REGISTER_ARGUMENT1_V2 0xAAC
#define AMD_PMF_REGISTER_ARGUMENT2_V2 0xAB0
/* Base address of SMU for mapping physical address to virtual address */
#define AMD_PMF_MAPPING_SIZE 0x01000
#define AMD_PMF_BASE_ADDR_OFFSET 0x10000
@ -179,7 +186,7 @@ static void __maybe_unused amd_pmf_dump_registers(struct amd_pmf_dev *dev)
value = amd_pmf_reg_read(dev, dev->smu_regs->resp_reg);
dev_dbg(dev->dev, "AMD_PMF_REGISTER_RESPONSE:%x\n", value);
value = amd_pmf_reg_read(dev, dev->smu_regs->arg_reg);
value = amd_pmf_reg_read(dev, dev->smu_regs->arg_reg[0]);
dev_dbg(dev->dev, "AMD_PMF_REGISTER_ARGUMENT:%d\n", value);
value = amd_pmf_reg_read(dev, dev->smu_regs->msg_reg);
@ -220,7 +227,7 @@ int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32
amd_pmf_reg_write(dev, dev->smu_regs->resp_reg, 0);
/* Write argument into argument register */
amd_pmf_reg_write(dev, dev->smu_regs->arg_reg, arg);
amd_pmf_reg_write(dev, dev->smu_regs->arg_reg[0], arg);
/* Write message ID to message ID register */
amd_pmf_reg_write(dev, dev->smu_regs->msg_reg, message);
@ -239,7 +246,7 @@ int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32
if (get) {
/* PMFW may take longer time to return back the data */
usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
*data = amd_pmf_reg_read(dev, dev->smu_regs->arg_reg);
*data = amd_pmf_reg_read(dev, dev->smu_regs->arg_reg[0]);
}
break;
case AMD_PMF_RESULT_CMD_REJECT_BUSY:
@ -266,7 +273,18 @@ int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32
static const struct amd_pmf_smu_regs amd_pmf_smu_regs_v1 = {
.msg_reg = AMD_PMF_REGISTER_MESSAGE,
.resp_reg = AMD_PMF_REGISTER_RESPONSE,
.arg_reg = AMD_PMF_REGISTER_ARGUMENT,
.arg_reg = { AMD_PMF_REGISTER_ARGUMENT, 0, 0 },
};
/* 1AH_M80H uses an extended mailbox with three argument registers */
static const struct amd_pmf_smu_regs amd_pmf_smu_regs_v2 = {
.msg_reg = AMD_PMF_REGISTER_MESSAGE_V2,
.resp_reg = AMD_PMF_REGISTER_RESPONSE_V2,
.arg_reg = {
AMD_PMF_REGISTER_ARGUMENT0_V2,
AMD_PMF_REGISTER_ARGUMENT1_V2,
AMD_PMF_REGISTER_ARGUMENT2_V2,
},
};
static const struct pci_device_id pmf_pci_ids[] = {
@ -274,6 +292,7 @@ static const struct pci_device_id pmf_pci_ids[] = {
{ PCI_DEVICE_DATA(AMD, CPU_ID_PS, &amd_pmf_smu_regs_v1) },
{ PCI_DEVICE_DATA(AMD, 1AH_M20H_ROOT, &amd_pmf_smu_regs_v1) },
{ PCI_DEVICE_DATA(AMD, 1AH_M60H_ROOT, &amd_pmf_smu_regs_v1) },
{ PCI_DEVICE_DATA(AMD, 1AH_M80H_ROOT, &amd_pmf_smu_regs_v2) },
{ }
};
@ -563,6 +582,7 @@ static const struct acpi_device_id amd_pmf_acpi_ids[] = {
{"AMDI0105", 0},
{"AMDI0107", 0},
{"AMDI0108", 0},
{"AMDI0109", 0},
{ }
};
MODULE_DEVICE_TABLE(acpi, amd_pmf_acpi_ids);

3
drivers/platform/x86/amd/pmf/pmf.h
View File

@ -28,6 +28,7 @@
#define AMD_CPU_ID_PS 0x14e8
#define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507
#define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122
#define PCI_DEVICE_ID_AMD_1AH_M80H_ROOT 0x115b
/* Aliases required by PCI_DEVICE_DATA() macro naming convention */
#define PCI_DEVICE_ID_AMD_CPU_ID_RMB AMD_CPU_ID_RMB
@ -400,7 +401,7 @@ struct pmf_cbi_ring_buffer {
struct amd_pmf_smu_regs {
u32 msg_reg;
u32 resp_reg;
u32 arg_reg;
u32 arg_reg[3];
};
struct amd_pmf_dev {