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arm64: dts: exynos: Enable USB in Exynos850

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Add USB controller and USB PHY controller nodes for Exynos850 SoC.

The USB controller has next features:
  - Dual Role Device (DRD) controller
  - DWC3 compatible
  - Supports USB 2.0 host and USB 2.0 device interfaces
  - Supports  full-speed (12 Mbps) and high-speed (480 Mbps) modes with
    USB device 2.0 interface
  - Supports on-chip USB PHY transceiver
  - Supports up to 16 bi-directional endpoints (that includes control
    endpoint 0)
  - Complies with xHCI 1.00 specification

Only USB 2.0 is supported in Exynos850, so only UTMI+ PHY interface is
specified in "phys" property (index 0) and PIPE3 is omitted (index 1).

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20230825215445.28309-2-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Sam Protsenko 2023-08-25 16:54:44 -05:00 committed by Krzysztof Kozlowski
parent 0bb80ecc33
commit 2f911ca41e
1 changed files with 30 additions and 0 deletions
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30
arch/arm64/boot/dts/exynos/exynos850.dtsi
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@ -570,6 +570,36 @@ sysreg_cmgp: syscon@11c20000 {
clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>;
};
usbdrd: usb@13600000 {
compatible = "samsung,exynos850-dwusb3";
ranges = <0x0 0x13600000 0x10000>;
clocks = <&cmu_hsi CLK_GOUT_USB_BUS_EARLY_CLK>,
<&cmu_hsi CLK_GOUT_USB_REF_CLK>;
clock-names = "bus_early", "ref";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
usbdrd_dwc3: usb@0 {
compatible = "snps,dwc3";
reg = <0x0 0x10000>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbdrd_phy 0>;
phy-names = "usb2-phy";
};
};
usbdrd_phy: phy@135d0000 {
compatible = "samsung,exynos850-usbdrd-phy";
reg = <0x135d0000 0x100>;
clocks = <&cmu_hsi CLK_GOUT_USB_PHY_ACLK>,
<&cmu_hsi CLK_GOUT_USB_PHY_REF_CLK>;
clock-names = "phy", "ref";
samsung,pmu-syscon = <&pmu_system_controller>;
#phy-cells = <1>;
status = "disabled";
};
usi_uart: usi@138200c0 {
compatible = "samsung,exynos850-usi";
reg = <0x138200c0 0x20>;