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irqchip/renesas-rzg2l: Drop IRQC_NUM_IRQ macro
The total number of interrupts in RZ/G2L and RZ/G3L SoC are different. Introduce struct rzg2l_hw_info to handle the hardware differences and replace the macro IRQC_NUM_IRQ with num_irq variable in struct rzg2l_hw_info. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260325192451.172562-13-biju.das.jz@bp.renesas.com
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b8e06e4e41
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2f81477895
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@ -24,7 +24,6 @@
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#define IRQC_IRQ_COUNT 8
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#define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT)
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#define IRQC_TINT_COUNT 32
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#define IRQC_NUM_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT)
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#define ISCR 0x10
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#define IITSR 0x14
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@ -68,6 +67,14 @@ struct rzg2l_irqc_reg_cache {
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u32 titsr[2];
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};
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/**
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* struct rzg2l_hw_info - Interrupt Control Unit controller hardware info structure.
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* @num_irq: Total Number of interrupts
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*/
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struct rzg2l_hw_info {
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unsigned int num_irq;
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};
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/**
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* struct rzg2l_irqc_priv - IRQ controller private data structure
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* @base: Controller's base address
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@ -75,6 +82,7 @@ struct rzg2l_irqc_reg_cache {
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* @tint_chip: Pointer to struct irq_chip for tint
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* @fwspec: IRQ firmware specific data
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* @lock: Lock to serialize access to hardware registers
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* @info: Hardware specific data
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* @cache: Registers cache for suspend/resume
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*/
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static struct rzg2l_irqc_priv {
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@ -83,6 +91,7 @@ static struct rzg2l_irqc_priv {
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const struct irq_chip *tint_chip;
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struct irq_fwspec *fwspec;
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raw_spinlock_t lock;
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struct rzg2l_hw_info info;
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struct rzg2l_irqc_reg_cache cache;
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} *rzg2l_irqc_data;
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@ -571,7 +580,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq,
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chip = priv->irq_chip;
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}
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if (hwirq > (IRQC_NUM_IRQ - 1))
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if (hwirq >= priv->info.num_irq)
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return -EINVAL;
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ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip, (void *)(uintptr_t)tint);
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@ -594,7 +603,7 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv,
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unsigned int i;
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int ret;
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for (i = 0; i < IRQC_NUM_IRQ; i++) {
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for (i = 0; i < priv->info.num_irq; i++) {
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ret = of_irq_parse_one(np, i, &map);
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if (ret)
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return ret;
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@ -607,7 +616,8 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv,
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static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct device_node *parent,
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const struct irq_chip *irq_chip,
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const struct irq_chip *tint_chip)
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const struct irq_chip *tint_chip,
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const struct rzg2l_hw_info info)
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{
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struct irq_domain *irq_domain, *parent_domain;
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struct device_node *node = pdev->dev.of_node;
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@ -630,7 +640,9 @@ static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct device_n
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if (IS_ERR(rzg2l_irqc_data->base))
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return PTR_ERR(rzg2l_irqc_data->base);
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rzg2l_irqc_data->fwspec = devm_kcalloc(&pdev->dev, IRQC_NUM_IRQ,
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rzg2l_irqc_data->info = info;
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rzg2l_irqc_data->fwspec = devm_kcalloc(&pdev->dev, info.num_irq,
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sizeof(*rzg2l_irqc_data->fwspec), GFP_KERNEL);
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if (!rzg2l_irqc_data->fwspec)
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return -ENOMEM;
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@ -655,7 +667,7 @@ static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct device_n
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raw_spin_lock_init(&rzg2l_irqc_data->lock);
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irq_domain = irq_domain_create_hierarchy(parent_domain, 0, IRQC_NUM_IRQ, dev_fwnode(dev),
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irq_domain = irq_domain_create_hierarchy(parent_domain, 0, info.num_irq, dev_fwnode(dev),
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&rzg2l_irqc_domain_ops, rzg2l_irqc_data);
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if (!irq_domain) {
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pm_runtime_put_sync(dev);
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@ -667,14 +679,20 @@ static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct device_n
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return 0;
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}
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static const struct rzg2l_hw_info rzg2l_hw_params = {
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.num_irq = IRQC_IRQ_START + IRQC_IRQ_COUNT + IRQC_TINT_COUNT,
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};
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static int rzg2l_irqc_probe(struct platform_device *pdev, struct device_node *parent)
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{
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return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_irq_chip, &rzg2l_irqc_tint_chip);
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return rzg2l_irqc_common_probe(pdev, parent, &rzg2l_irqc_irq_chip, &rzg2l_irqc_tint_chip,
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rzg2l_hw_params);
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}
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static int rzfive_irqc_probe(struct platform_device *pdev, struct device_node *parent)
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{
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return rzg2l_irqc_common_probe(pdev, parent, &rzfive_irqc_irq_chip, &rzfive_irqc_tint_chip);
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return rzg2l_irqc_common_probe(pdev, parent, &rzfive_irqc_irq_chip, &rzfive_irqc_tint_chip,
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rzg2l_hw_params);
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}
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IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc)
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