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arm64: dts: qcom: Add MST pixel streams for displayport

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Update Qualcomm DT files in order to declare extra stream pixel clocks
and extra register resources used on these platforms to support
DisplayPort MST.

The driver will continue to work with the old DTS files as even after
adding MST support the driver will have to support old DTS files which
didn't have MST clocks.

Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250916-dp_mst_bindings-v9-2-68c674b39d8e@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Jessica Zhang 2025-09-16 20:18:29 +03:00 committed by Bjorn Andersson
parent f2983d8a1e
commit 2f695d3eac
13 changed files with 185 additions and 74 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
arch/arm64/boot/dts/qcom/lemans.dtsi
View File

@ -5070,7 +5070,11 @@ mdss0_dp0: displayport-controller@af54000 {
<0x0 0x0af54200 0x0 0x0c0>,
<0x0 0x0af55000 0x0 0x770>,
<0x0 0x0af56000 0x0 0x09c>,
<0x0 0x0af57000 0x0 0x09c>;
<0x0 0x0af57000 0x0 0x09c>,
<0x0 0x0af58000 0x0 0x09c>,
<0x0 0x0af59000 0x0 0x09c>,
<0x0 0x0af5a000 0x0 0x23c>,
<0x0 0x0af5b000 0x0 0x23c>;
interrupt-parent = <&mdss0>;
interrupts = <12>;
@ -5079,15 +5083,28 @@ mdss0_dp0: displayport-controller@af54000 {
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
"stream_pixel",
"stream_1_pixel",
"stream_2_pixel",
"stream_3_pixel";
assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
assigned-clock-parents = <&mdss0_dp0_phy 0>,
<&mdss0_dp0_phy 1>,
<&mdss0_dp0_phy 1>,
<&mdss0_dp0_phy 1>,
<&mdss0_dp0_phy 1>;
phys = <&mdss0_dp0_phy>;
phy-names = "dp";
@ -5149,7 +5166,11 @@ mdss0_dp1: displayport-controller@af5c000 {
<0x0 0x0af5c200 0x0 0x0c0>,
<0x0 0x0af5d000 0x0 0x770>,
<0x0 0x0af5e000 0x0 0x09c>,
<0x0 0x0af5f000 0x0 0x09c>;
<0x0 0x0af5f000 0x0 0x09c>,
<0x0 0x0af60000 0x0 0x09c>,
<0x0 0x0af61000 0x0 0x09c>,
<0x0 0x0af62000 0x0 0x23c>,
<0x0 0x0af63000 0x0 0x23c>;
interrupt-parent = <&mdss0>;
interrupts = <13>;
@ -5158,15 +5179,20 @@ mdss0_dp1: displayport-controller@af5c000 {
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
"stream_pixel",
"stream_1_pixel";
assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
assigned-clock-parents = <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>;
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&mdss0_dp1_phy 0>,
<&mdss0_dp1_phy 1>,
<&mdss0_dp1_phy 1>;
phys = <&mdss0_dp1_phy>;
phy-names = "dp";

10
arch/arm64/boot/dts/qcom/sar2130p.dtsi
View File

@ -2144,16 +2144,20 @@ mdss_dp0: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
"stream_pixel",
"stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;

3
arch/arm64/boot/dts/qcom/sc7280.dtsi
View File

@ -5144,7 +5144,8 @@ mdss_edp: edp@aea0000 {
reg = <0 0x0aea0000 0 0x200>,
<0 0x0aea0200 0 0x200>,
<0 0x0aea0400 0 0xc00>,
<0 0x0aea1000 0 0x400>;
<0 0x0aea1000 0 0x400>,
<0 0x0aea1400 0 0x400>;
interrupt-parent = <&mdss>;
interrupts = <14>;

23
arch/arm64/boot/dts/qcom/sc8180x.dtsi
View File

@ -3256,16 +3256,20 @@ mdss_dp0: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
"stream_pixel",
"stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>;
@ -3334,16 +3338,20 @@ mdss_dp1: displayport-controller@ae98000 {
<&dispcc DISP_CC_MDSS_DP_AUX1_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK1_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>;
<&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>,
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
"stream_pixel",
"stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>;
<&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>;
@ -3404,7 +3412,8 @@ mdss_edp: displayport-controller@ae9a000 {
reg = <0 0xae9a000 0 0x200>,
<0 0xae9a200 0 0x200>,
<0 0xae9a400 0 0x600>,
<0 0xae9aa00 0 0x400>;
<0 0xae9aa00 0 0x400>,
<0 0xae9b000 0 0x400>;
interrupt-parent = <&mdss>;
interrupts = <14>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

72
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View File

@ -4706,15 +4706,19 @@ mdss0_dp0: displayport-controller@ae90000 {
<&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
<&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
"stream_pixel",
"stream_1_pixel";
assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
<&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
<&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
<&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>;
@ -4785,14 +4789,18 @@ mdss0_dp1: displayport-controller@ae98000 {
<&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
<&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
"ctrl_link_iface", "stream_pixel";
"ctrl_link_iface", "stream_pixel",
"stream_1_pixel";
assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
<&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
<&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
<&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
@ -4862,10 +4870,12 @@ mdss0_dp2: displayport-controller@ae9a000 {
<&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
<&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
"ctrl_link_iface", "stream_pixel";
"ctrl_link_iface", "stream_pixel",
"stream_1_pixel";
interrupt-parent = <&mdss0>;
interrupts = <14>;
phys = <&mdss0_dp2_phy>;
@ -4873,8 +4883,11 @@ mdss0_dp2: displayport-controller@ae9a000 {
power-domains = <&rpmhpd SC8280XP_MMCX>;
assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
<&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
<&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
<&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&mdss0_dp2_phy 0>,
<&mdss0_dp2_phy 1>,
<&mdss0_dp2_phy 1>;
operating-points-v2 = <&mdss0_dp2_opp_table>;
#sound-dai-cells = <0>;
@ -6043,10 +6056,12 @@ mdss1_dp0: displayport-controller@22090000 {
<&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
<&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
"ctrl_link_iface", "stream_pixel";
"ctrl_link_iface", "stream_pixel",
"stream_1_pixel";
interrupt-parent = <&mdss1>;
interrupts = <12>;
phys = <&mdss1_dp0_phy>;
@ -6054,8 +6069,11 @@ mdss1_dp0: displayport-controller@22090000 {
power-domains = <&rpmhpd SC8280XP_MMCX>;
assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
<&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
<&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
<&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&mdss1_dp0_phy 0>,
<&mdss1_dp0_phy 1>,
<&mdss1_dp0_phy 1>;
operating-points-v2 = <&mdss1_dp0_opp_table>;
#sound-dai-cells = <0>;
@ -6118,10 +6136,12 @@ mdss1_dp1: displayport-controller@22098000 {
<&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
<&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
"ctrl_link_iface", "stream_pixel";
"ctrl_link_iface", "stream_pixel",
"stream_1_pixel";
interrupt-parent = <&mdss1>;
interrupts = <13>;
phys = <&mdss1_dp1_phy>;
@ -6129,8 +6149,11 @@ mdss1_dp1: displayport-controller@22098000 {
power-domains = <&rpmhpd SC8280XP_MMCX>;
assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
<&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
<&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
<&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&mdss1_dp1_phy 0>,
<&mdss1_dp1_phy 1>,
<&mdss1_dp1_phy 1>;
operating-points-v2 = <&mdss1_dp1_opp_table>;
#sound-dai-cells = <0>;
@ -6193,10 +6216,12 @@ mdss1_dp2: displayport-controller@2209a000 {
<&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
<&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
"ctrl_link_iface", "stream_pixel";
"ctrl_link_iface", "stream_pixel",
"stream_1_pixel";
interrupt-parent = <&mdss1>;
interrupts = <14>;
phys = <&mdss1_dp2_phy>;
@ -6204,8 +6229,11 @@ mdss1_dp2: displayport-controller@2209a000 {
power-domains = <&rpmhpd SC8280XP_MMCX>;
assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
<&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
<&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
<&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&mdss1_dp2_phy 0>,
<&mdss1_dp2_phy 1>,
<&mdss1_dp2_phy 1>;
operating-points-v2 = <&mdss1_dp2_opp_table>;
#sound-dai-cells = <0>;

15
arch/arm64/boot/dts/qcom/sdm845.dtsi
View File

@ -4656,12 +4656,19 @@ mdss_dp: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
clock-names = "core_iface", "core_aux", "ctrl_link",
"ctrl_link_iface", "stream_pixel";
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel",
"stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";

10
arch/arm64/boot/dts/qcom/sm8150.dtsi
View File

@ -3890,16 +3890,20 @@ mdss_dp: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
"stream_pixel",
"stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;

10
arch/arm64/boot/dts/qcom/sm8250.dtsi
View File

@ -4771,16 +4771,20 @@ mdss_dp: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
"stream_pixel",
"stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;

10
arch/arm64/boot/dts/qcom/sm8350.dtsi
View File

@ -2876,16 +2876,20 @@ mdss_dp: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
"stream_pixel",
"stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;

10
arch/arm64/boot/dts/qcom/sm8450.dtsi
View File

@ -3434,16 +3434,20 @@ mdss_dp0: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
"stream_pixel",
"stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;

10
arch/arm64/boot/dts/qcom/sm8550.dtsi
View File

@ -3759,16 +3759,20 @@ mdss_dp0: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
"stream_pixel",
"stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;

10
arch/arm64/boot/dts/qcom/sm8650.dtsi
View File

@ -5660,16 +5660,20 @@ mdss_dp0: displayport-controller@af54000 {
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
"stream_pixel",
"stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
operating-points-v2 = <&dp_opp_table>;

30
arch/arm64/boot/dts/qcom/x1e80100.dtsi
View File

@ -5476,16 +5476,20 @@ mdss_dp0: displayport-controller@ae90000 {
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
"stream_pixel",
"stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
operating-points-v2 = <&mdss_dp0_opp_table>;
@ -5560,16 +5564,20 @@ mdss_dp1: displayport-controller@ae98000 {
<&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
<&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
<&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
"stream_pixel",
"stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
<&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
operating-points-v2 = <&mdss_dp1_opp_table>;
@ -5644,16 +5652,20 @@ mdss_dp2: displayport-controller@ae9a000 {
<&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
<&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
<&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
"stream_pixel",
"stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
<&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
operating-points-v2 = <&mdss_dp2_opp_table>;