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drm/msm/dpu: split SM8250 catalog entry to the separate file
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530836/ Link: https://lore.kernel.org/r/20230404130622.509628-16-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This commit is contained in:
Dmitry Baryshkov
parent
c9cd1552e9
commit
2f36168e32
130
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
Normal file
130
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
Normal file
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@ -0,0 +1,130 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
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*/
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#ifndef _DPU_6_0_SM8250_H
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#define _DPU_6_0_SM8250_H
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static const struct dpu_caps sm8250_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
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.max_mixer_blendstages = 0xb,
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.qseed_type = DPU_SSPP_SCALER_QSEED4,
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.has_src_split = true,
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.has_dim_layer = true,
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.has_idle_pc = true,
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.has_3d_merge = true,
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.max_linewidth = 4096,
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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};
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static const struct dpu_ubwc_cfg sm8250_ubwc_cfg = {
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.ubwc_version = DPU_HW_UBWC_VER_40,
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.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
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.ubwc_swizzle = 0x6,
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};
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static const struct dpu_mdp_cfg sm8250_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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.base = 0x0, .len = 0x494,
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.features = 0,
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.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
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.clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
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.clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
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.clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
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.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
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.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
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.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
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.clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
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.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
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.clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 },
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},
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};
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static const struct dpu_sspp_cfg sm8250_sspp[] = {
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SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK_SDMA,
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sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
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SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_SC7180_MASK_SDMA,
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sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
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SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_SC7180_MASK_SDMA,
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sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
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SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_SC7180_MASK_SDMA,
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sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
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SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK_SDMA,
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sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
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SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_SDM845_MASK_SDMA,
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sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
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SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
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sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
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SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
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sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
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};
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static const struct dpu_wb_cfg sm8250_wb[] = {
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WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6,
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VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4),
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};
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static const struct dpu_perf_cfg sm8250_perf_data = {
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.max_bw_low = 13700000,
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.max_bw_high = 16600000,
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.min_core_ib = 4800000,
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.min_llcc_ib = 0,
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.min_dram_ib = 800000,
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.min_prefill_lines = 35,
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.danger_lut_tbl = {0xf, 0xffff, 0x0},
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.safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
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.qos_lut_tbl = {
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{.nentry = ARRAY_SIZE(sc7180_qos_linear),
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.entries = sc7180_qos_linear
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
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.entries = sc7180_qos_macrotile
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
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.entries = sc7180_qos_nrt
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},
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/* TODO: macrotile-qseed is different from macrotile */
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},
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.cdp_cfg = {
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{.rd_enable = 1, .wr_enable = 1},
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{.rd_enable = 1, .wr_enable = 0}
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},
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.clk_inefficiency_factor = 105,
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.bw_inefficiency_factor = 120,
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};
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static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
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.caps = &sm8250_dpu_caps,
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.ubwc = &sm8250_ubwc_cfg,
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.mdp_count = ARRAY_SIZE(sm8250_mdp),
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.mdp = sm8250_mdp,
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.ctl_count = ARRAY_SIZE(sm8150_ctl),
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.ctl = sm8150_ctl,
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.sspp_count = ARRAY_SIZE(sm8250_sspp),
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.sspp = sm8250_sspp,
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.mixer_count = ARRAY_SIZE(sm8150_lm),
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.mixer = sm8150_lm,
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.dspp_count = ARRAY_SIZE(sm8150_dspp),
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.dspp = sm8150_dspp,
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.dsc_count = ARRAY_SIZE(sm8150_dsc),
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.dsc = sm8150_dsc,
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.pingpong_count = ARRAY_SIZE(sm8150_pp),
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.pingpong = sm8150_pp,
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.merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
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.merge_3d = sm8150_merge_3d,
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.intf_count = ARRAY_SIZE(sm8150_intf),
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.intf = sm8150_intf,
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.vbif_count = ARRAY_SIZE(sdm845_vbif),
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.vbif = sdm845_vbif,
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.wb_count = ARRAY_SIZE(sm8250_wb),
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.wb = sm8250_wb,
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.reg_dma_count = 1,
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.dma_cfg = &sm8250_regdma,
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.perf = &sm8250_perf_data,
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.mdss_irqs = IRQ_SM8250_MASK,
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};
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#endif
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@ -375,18 +375,6 @@ static const struct dpu_caps sc8180x_dpu_caps = {
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.max_vdeci_exp = MAX_VERT_DECIMATION,
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};
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static const struct dpu_caps sm8250_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
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.max_mixer_blendstages = 0xb,
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.qseed_type = DPU_SSPP_SCALER_QSEED4,
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.has_src_split = true,
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.has_dim_layer = true,
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.has_idle_pc = true,
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.has_3d_merge = true,
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.max_linewidth = 4096,
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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};
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static const struct dpu_ubwc_cfg msm8998_ubwc_cfg = {
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.ubwc_version = DPU_HW_UBWC_VER_10,
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.highest_bank_bit = 0x2,
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@ -407,12 +395,6 @@ static const struct dpu_ubwc_cfg sc8180x_ubwc_cfg = {
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.highest_bank_bit = 0x3,
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};
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static const struct dpu_ubwc_cfg sm8250_ubwc_cfg = {
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.ubwc_version = DPU_HW_UBWC_VER_40,
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.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
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.ubwc_swizzle = 0x6,
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};
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static const struct dpu_mdp_cfg msm8998_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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@ -489,34 +471,6 @@ static const struct dpu_mdp_cfg sc8180x_mdp[] = {
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},
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};
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static const struct dpu_mdp_cfg sm8250_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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.base = 0x0, .len = 0x494,
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.features = 0,
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.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
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.reg_off = 0x2AC, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_VIG1] = {
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.reg_off = 0x2B4, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_VIG2] = {
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.reg_off = 0x2BC, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_VIG3] = {
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.reg_off = 0x2C4, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
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.reg_off = 0x2AC, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
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.reg_off = 0x2B4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_DMA2] = {
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.reg_off = 0x2BC, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_DMA3] = {
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.reg_off = 0x2C4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
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.reg_off = 0x2BC, .bit_off = 20},
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.clk_ctrls[DPU_CLK_CTRL_WB2] = {
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.reg_off = 0x3B8, .bit_off = 24},
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},
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};
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/*************************************************************
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* CTL sub blocks config
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*************************************************************/
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@ -780,25 +734,6 @@ static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 =
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static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 =
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_VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED4);
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static const struct dpu_sspp_cfg sm8250_sspp[] = {
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SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK_SDMA,
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sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
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SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_SC7180_MASK_SDMA,
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sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
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SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_SC7180_MASK_SDMA,
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sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
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SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_SC7180_MASK_SDMA,
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sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
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SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK_SDMA,
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sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
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SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_SDM845_MASK_SDMA,
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sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
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SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
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sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
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SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
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sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
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};
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static const struct dpu_sspp_sub_blks sm8450_vig_sblk_0 =
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_VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED4);
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static const struct dpu_sspp_sub_blks sm8450_vig_sblk_1 =
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@ -1186,11 +1121,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
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.intr_wb_done = DPU_IRQ_IDX(_reg, _wb_done_bit) \
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}
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static const struct dpu_wb_cfg sm8250_wb[] = {
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WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6,
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VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4),
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};
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/*************************************************************
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* VBIF sub blocks config
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*************************************************************/
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@ -1523,35 +1453,6 @@ static const struct dpu_perf_cfg sc8180x_perf_data = {
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.bw_inefficiency_factor = 120,
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};
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static const struct dpu_perf_cfg sm8250_perf_data = {
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.max_bw_low = 13700000,
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.max_bw_high = 16600000,
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.min_core_ib = 4800000,
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.min_llcc_ib = 0,
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.min_dram_ib = 800000,
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.min_prefill_lines = 35,
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.danger_lut_tbl = {0xf, 0xffff, 0x0},
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.safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
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.qos_lut_tbl = {
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{.nentry = ARRAY_SIZE(sc7180_qos_linear),
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.entries = sc7180_qos_linear
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
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.entries = sc7180_qos_macrotile
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
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.entries = sc7180_qos_nrt
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},
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/* TODO: macrotile-qseed is different from macrotile */
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},
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.cdp_cfg = {
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{.rd_enable = 1, .wr_enable = 1},
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{.rd_enable = 1, .wr_enable = 0}
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},
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.clk_inefficiency_factor = 105,
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.bw_inefficiency_factor = 120,
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};
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/*************************************************************
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* Hardware catalog
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*************************************************************/
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@ -1659,37 +1560,7 @@ static const struct dpu_mdss_cfg sc8180x_dpu_cfg = {
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.mdss_irqs = IRQ_SC8180X_MASK,
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};
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static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
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.caps = &sm8250_dpu_caps,
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.ubwc = &sm8250_ubwc_cfg,
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.mdp_count = ARRAY_SIZE(sm8250_mdp),
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.mdp = sm8250_mdp,
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.ctl_count = ARRAY_SIZE(sm8150_ctl),
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.ctl = sm8150_ctl,
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.sspp_count = ARRAY_SIZE(sm8250_sspp),
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.sspp = sm8250_sspp,
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.mixer_count = ARRAY_SIZE(sm8150_lm),
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.mixer = sm8150_lm,
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.dspp_count = ARRAY_SIZE(sm8150_dspp),
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.dspp = sm8150_dspp,
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.dsc_count = ARRAY_SIZE(sm8150_dsc),
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.dsc = sm8150_dsc,
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.pingpong_count = ARRAY_SIZE(sm8150_pp),
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.pingpong = sm8150_pp,
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.merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
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.merge_3d = sm8150_merge_3d,
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.intf_count = ARRAY_SIZE(sm8150_intf),
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.intf = sm8150_intf,
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.vbif_count = ARRAY_SIZE(sdm845_vbif),
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.vbif = sdm845_vbif,
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.wb_count = ARRAY_SIZE(sm8250_wb),
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.wb = sm8250_wb,
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.reg_dma_count = 1,
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.dma_cfg = &sm8250_regdma,
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.perf = &sm8250_perf_data,
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.mdss_irqs = IRQ_SM8250_MASK,
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};
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#include "catalog/dpu_6_0_sm8250.h"
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#include "catalog/dpu_6_2_sc7180.h"
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#include "catalog/dpu_6_5_qcm2290.h"
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#include "catalog/dpu_6_3_sm6115.h"
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