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pinctrl: rockchip: add rk3562 support
Add support for the 5 GPIO banks in the rk3562. Signed-off-by: Steven Liu <steven.liu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/20241224093620.3815705-1-kever.yang@rock-chips.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Steven Liu
Linus Walleij
parent
1dc7fd41e8
commit
2f0ffa57f6
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@ -1,7 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Pinctrl driver for Rockchip SoCs
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*
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* Copyright (c) 2020-2024 Rockchip Electronics Co., Ltd.
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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@ -2003,6 +2003,151 @@ static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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return 0;
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}
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#define RK3562_DRV_BITS_PER_PIN 8
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#define RK3562_DRV_PINS_PER_REG 2
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#define RK3562_DRV_GPIO0_OFFSET 0x20070
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#define RK3562_DRV_GPIO1_OFFSET 0x200
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#define RK3562_DRV_GPIO2_OFFSET 0x240
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#define RK3562_DRV_GPIO3_OFFSET 0x10280
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#define RK3562_DRV_GPIO4_OFFSET 0x102C0
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static int rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl *info = bank->drvdata;
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*regmap = info->regmap_base;
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switch (bank->bank_num) {
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case 0:
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*reg = RK3562_DRV_GPIO0_OFFSET;
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break;
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case 1:
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*reg = RK3562_DRV_GPIO1_OFFSET;
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break;
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case 2:
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*reg = RK3562_DRV_GPIO2_OFFSET;
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break;
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case 3:
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*reg = RK3562_DRV_GPIO3_OFFSET;
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break;
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case 4:
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*reg = RK3562_DRV_GPIO4_OFFSET;
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break;
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default:
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dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
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break;
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}
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*reg += ((pin_num / RK3562_DRV_PINS_PER_REG) * 4);
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*bit = pin_num % RK3562_DRV_PINS_PER_REG;
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*bit *= RK3562_DRV_BITS_PER_PIN;
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return 0;
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}
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#define RK3562_PULL_BITS_PER_PIN 2
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#define RK3562_PULL_PINS_PER_REG 8
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#define RK3562_PULL_GPIO0_OFFSET 0x20020
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#define RK3562_PULL_GPIO1_OFFSET 0x80
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#define RK3562_PULL_GPIO2_OFFSET 0x90
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#define RK3562_PULL_GPIO3_OFFSET 0x100A0
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#define RK3562_PULL_GPIO4_OFFSET 0x100B0
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static int rk3562_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl *info = bank->drvdata;
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*regmap = info->regmap_base;
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switch (bank->bank_num) {
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case 0:
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*reg = RK3562_PULL_GPIO0_OFFSET;
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break;
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case 1:
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*reg = RK3562_PULL_GPIO1_OFFSET;
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break;
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case 2:
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*reg = RK3562_PULL_GPIO2_OFFSET;
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break;
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case 3:
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*reg = RK3562_PULL_GPIO3_OFFSET;
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break;
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case 4:
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*reg = RK3562_PULL_GPIO4_OFFSET;
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break;
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default:
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dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
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break;
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}
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*reg += ((pin_num / RK3562_PULL_PINS_PER_REG) * 4);
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*bit = pin_num % RK3562_PULL_PINS_PER_REG;
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*bit *= RK3562_PULL_BITS_PER_PIN;
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return 0;
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}
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#define RK3562_SMT_BITS_PER_PIN 2
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#define RK3562_SMT_PINS_PER_REG 8
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#define RK3562_SMT_GPIO0_OFFSET 0x20030
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#define RK3562_SMT_GPIO1_OFFSET 0xC0
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#define RK3562_SMT_GPIO2_OFFSET 0xD0
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#define RK3562_SMT_GPIO3_OFFSET 0x100E0
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#define RK3562_SMT_GPIO4_OFFSET 0x100F0
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static int rk3562_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num,
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struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl *info = bank->drvdata;
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*regmap = info->regmap_base;
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switch (bank->bank_num) {
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case 0:
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*reg = RK3562_SMT_GPIO0_OFFSET;
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break;
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case 1:
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*reg = RK3562_SMT_GPIO1_OFFSET;
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break;
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case 2:
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*reg = RK3562_SMT_GPIO2_OFFSET;
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break;
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case 3:
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*reg = RK3562_SMT_GPIO3_OFFSET;
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break;
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case 4:
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*reg = RK3562_SMT_GPIO4_OFFSET;
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break;
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default:
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dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
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break;
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}
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*reg += ((pin_num / RK3562_SMT_PINS_PER_REG) * 4);
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*bit = pin_num % RK3562_SMT_PINS_PER_REG;
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*bit *= RK3562_SMT_BITS_PER_PIN;
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return 0;
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}
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#define RK3568_PULL_PMU_OFFSET 0x20
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#define RK3568_PULL_GRF_OFFSET 0x80
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#define RK3568_PULL_BITS_PER_PIN 2
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@ -2495,7 +2640,8 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
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rmask_bits = RK3588_DRV_BITS_PER_PIN;
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ret = strength;
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goto config;
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} else if (ctrl->type == RK3568) {
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} else if (ctrl->type == RK3562 ||
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ctrl->type == RK3568) {
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rmask_bits = RK3568_DRV_BITS_PER_PIN;
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ret = (1 << (strength + 1)) - 1;
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goto config;
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@ -2639,6 +2785,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
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case RK3328:
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case RK3368:
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case RK3399:
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case RK3562:
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case RK3568:
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case RK3576:
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case RK3588:
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@ -2699,6 +2846,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
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case RK3328:
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case RK3368:
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case RK3399:
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case RK3562:
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case RK3568:
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case RK3576:
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case RK3588:
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@ -2810,6 +2958,7 @@ static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
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data >>= bit;
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switch (ctrl->type) {
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case RK3562:
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case RK3568:
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return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
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default:
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@ -2839,6 +2988,7 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
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/* enable the write to the equivalent lower bits */
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switch (ctrl->type) {
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case RK3562:
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case RK3568:
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data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
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rmask = data | (data >> 16);
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@ -2965,6 +3115,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
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case RK3328:
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case RK3368:
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case RK3399:
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case RK3562:
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case RK3568:
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case RK3576:
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case RK3588:
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@ -4086,6 +4237,49 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
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.drv_calc_reg = rk3399_calc_drv_reg_and_bit,
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};
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static struct rockchip_pin_bank rk3562_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0x20000, 0x20008, 0x20010, 0x20018),
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PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0, 0x08, 0x10, 0x18),
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PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0x20, 0, 0, 0),
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PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0x10040, 0x10048, 0x10050, 0x10058),
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PIN_BANK_IOMUX_FLAGS_OFFSET(4, 16, "gpio4",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0,
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0,
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0x10060, 0x10068, 0, 0),
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};
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static struct rockchip_pin_ctrl rk3562_pin_ctrl __maybe_unused = {
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.pin_banks = rk3562_pin_banks,
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.nr_banks = ARRAY_SIZE(rk3562_pin_banks),
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.label = "RK3562-GPIO",
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.type = RK3562,
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.pull_calc_reg = rk3562_calc_pull_reg_and_bit,
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.drv_calc_reg = rk3562_calc_drv_reg_and_bit,
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.schmitt_calc_reg = rk3562_calc_schmitt_reg_and_bit,
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};
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static struct rockchip_pin_bank rk3568_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
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IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
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@ -4210,6 +4404,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
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.data = &rk3368_pin_ctrl },
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{ .compatible = "rockchip,rk3399-pinctrl",
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.data = &rk3399_pin_ctrl },
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{ .compatible = "rockchip,rk3562-pinctrl",
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.data = &rk3562_pin_ctrl },
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{ .compatible = "rockchip,rk3568-pinctrl",
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.data = &rk3568_pin_ctrl },
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{ .compatible = "rockchip,rk3576-pinctrl",
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.
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* Copyright (c) 2020-2024 Rockchip Electronics Co., Ltd.
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*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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@ -196,6 +196,7 @@ enum rockchip_pinctrl_type {
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RK3328,
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RK3368,
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RK3399,
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RK3562,
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RK3568,
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RK3576,
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RK3588,
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