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drm/amdgpu: query the reserved info with get_fw_reserved_info

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Extend amdgpu_ttm_init_fw_resv_region() to honour the
->get_fw_reserved_info().

Previously the FW carveout was hardcoded and placed at the top of VRAM
(real_vram_size - reserve_size):
 - a hard-coded 144/256 MB for GC 12.1.0;
 - or DISCOVERY_TMR_OFFSET fallback.

The hard-coded GC 12.1.0 path is replaced by ->get_fw_reserved_info(),
which returns a (size, offset_within_VRAM) pair derived from the
MASTER_DIE_UMF_REGION embedded in IP discovery, and falls back only
when the discovery region is missing or invalid.

v1->v2: Remove !adev->bios check, and call the get_fw_reserved_info
    interface when it is available. (suggested by Hawking)

Suggested-by: Lijo Lazar <lijo.lazar@amd.com>
Suggested-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Feifei Xu 2026-05-12 10:39:11 +08:00 committed by Alex Deucher
parent afa9574fb5
commit 2eee94d2e0
1 changed files with 15 additions and 11 deletions
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26
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
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@ -1737,7 +1737,7 @@ void amdgpu_ttm_init_vram_resv(struct amdgpu_device *adev,
static void amdgpu_ttm_init_fw_resv_region(struct amdgpu_device *adev)
{
uint32_t reserve_size = 0;
u64 reserve_size = 0, offset = 0;
if (!adev->discovery.reserve_tmr)
return;
@ -1749,24 +1749,28 @@ static void amdgpu_ttm_init_fw_resv_region(struct amdgpu_device *adev)
* Otherwise, fallback to legacy approach to check and reserve tmr block for ip
* discovery data and G6 memory training data respectively
*/
if (adev->bios)
if (adev->bios) {
reserve_size =
amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
if (reserve_size)
offset = adev->gmc.real_vram_size - reserve_size;
}
if (!adev->bios &&
(amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) ||
amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) ||
amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)))
reserve_size = max(reserve_size, (uint32_t)280 << 20);
else if (!adev->bios &&
amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) {
reserve_size = max(reserve_size, (uint32_t)150 << 20);
} else if (!reserve_size)
amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0))) {
reserve_size = (u64)280 << 20;
offset = adev->gmc.real_vram_size - reserve_size;
} else if (adev->asic_funcs && adev->asic_funcs->get_fw_reserved_info) {
dev_dbg(adev->dev, "Querying FW reserved region info through get_fw_reserved_info\n");
adev->asic_funcs->get_fw_reserved_info(adev, &reserve_size, &offset);
} else if (!reserve_size) {
reserve_size = DISCOVERY_TMR_OFFSET;
offset = adev->gmc.real_vram_size - reserve_size;
}
amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW,
adev->gmc.real_vram_size - reserve_size,
reserve_size, false);
offset, reserve_size, false);
}
static void amdgpu_ttm_init_mem_train_resv_region(struct amdgpu_device *adev)