From 2e4806d2b78f1f4a7585fa1d14ab45f9a79316b7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 5 Nov 2023 21:06:15 +0100 Subject: [PATCH] clk: rs9: Fix DIF OEn bit placement on 9FGV0241 [ Upstream commit 29d861b5d29b6c80a887e93ad982cbbf4af2a06b ] On 9FGV0241, the DIF OE0 is BIT(1) and DIF OE1 is BIT(2), on the other chips like 9FGV0441 and 9FGV0841 DIF OE0 is BIT(0) and so on. Increment the index in BIT() macro instead of the result of BIT() macro to shift the bit correctly on 9FGV0241. Fixes: 603df193ec51 ("clk: rs9: Support device specific dif bit calculation") Signed-off-by: Marek Vasut Link: https://lore.kernel.org/r/20231105200642.62792-1-marek.vasut+renesas@mailbox.org Reviewed-by: Alexander Stein Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/clk-renesas-pcie.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-renesas-pcie.c b/drivers/clk/clk-renesas-pcie.c index 7d7b2cb75318..3b6ad2307a41 100644 --- a/drivers/clk/clk-renesas-pcie.c +++ b/drivers/clk/clk-renesas-pcie.c @@ -163,7 +163,7 @@ static u8 rs9_calc_dif(const struct rs9_driver_data *rs9, int idx) enum rs9_model model = rs9->chip_info->model; if (model == RENESAS_9FGV0241) - return BIT(idx) + 1; + return BIT(idx + 1); else if (model == RENESAS_9FGV0441) return BIT(idx);