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drm/i915: Nuke pointless div by 64bit

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Bunch of places use a 64bit divisor needlessly. Switch
to 32bit divisor.

Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200302143943.32676-1-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Ville Syrjälä 2020-03-02 16:39:38 +02:00
parent 8ca6d0237d
commit 2e2701582a
1 changed files with 5 additions and 6 deletions
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11
drivers/gpu/drm/i915/i915_perf.c
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@ -1612,10 +1612,9 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
struct drm_i915_gem_object *bo; struct drm_i915_gem_object *bo;
struct i915_vma *vma; struct i915_vma *vma;
const u64 delay_ticks = 0xffffffffffffffff - const u64 delay_ticks = 0xffffffffffffffff -
DIV64_U64_ROUND_UP( DIV_ROUND_UP_ULL(atomic64_read(&stream->perf->noa_programming_delay) *
atomic64_read(&stream->perf->noa_programming_delay) * RUNTIME_INFO(i915)->cs_timestamp_frequency_khz,
RUNTIME_INFO(i915)->cs_timestamp_frequency_khz, 1000000);
1000000ull);
const u32 base = stream->engine->mmio_base; const u32 base = stream->engine->mmio_base;
#define CS_GPR(x) GEN8_RING_CS_GPR(base, x) #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
u32 *batch, *ts0, *cs, *jump; u32 *batch, *ts0, *cs, *jump;
@ -3485,8 +3484,8 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent) static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
{ {
return div64_u64(1000000000ULL * (2ULL << exponent), return div_u64(1000000 * (2ULL << exponent),
1000ULL * RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_khz); RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_khz);
} }
/** /**