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MIPS: mobileye: dts: eyeq5: add the emmc controller

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Add the MMC/SDHCI controller found in the eyeQ5 SoC. It is based on the
cadence sd4hc controller and support modes up to HS400 enhanced strobe.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Benoît Monin 2025-06-17 15:25:55 +02:00 committed by Thomas Bogendoerfer
parent e1c98b1f5f
commit 2de84c70ff
1 changed files with 22 additions and 0 deletions
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22
arch/mips/boot/dts/mobileye/eyeq5.dtsi
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@ -178,6 +178,28 @@ timer {
clocks = <&olb EQ5C_CPU_CORE0>;
};
};
emmc: sdhci@2200000 {
compatible = "mobileye,eyeq-sd4hc", "cdns,sd4hc";
reg = <0 0x2200000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&olb EQ5C_PER_EMMC>;
bus-width = <8>;
max-frequency = <200000000>;
mmc-ddr-1_8v;
sd-uhs-ddr50;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
cdns,phy-input-delay-legacy = <4>;
cdns,phy-input-delay-mmc-highspeed = <2>;
cdns,phy-input-delay-mmc-ddr = <3>;
cdns,phy-dll-delay-sdclk = <32>;
cdns,phy-dll-delay-sdclk-hsmmc = <32>;
cdns,phy-dll-delay-strobe = <32>;
};
};
};