From 80323742eab6aca28ebe91cbca84a3d5ab940f4d Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Fri, 29 Aug 2014 19:11:50 +0300 Subject: [PATCH 1/5] ARM: OMAP2+: gpmc: Print error message in set_gpmc_timing_reg() Simplify set_gpmc_timing_reg() and always print error message if the requested timing cannot be achieved due to a too fast GPMC functional clock, irrespective if whether DEBUG is defined or not. This should help us debug timing configuration issues, which were otherwise simply not being displayed in the kernel log. Signed-off-by: Roger Quadros Signed-off-by: Sekhar Nori Acked-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc.c | 23 ++++++----------------- 1 file changed, 6 insertions(+), 17 deletions(-) diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 5fa3755261ce..45f680f965ed 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -283,13 +283,8 @@ static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p) p->cycle2cyclediffcsen); } -#ifdef DEBUG static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int time, const char *name) -#else -static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, - int time) -#endif { u32 l; int ticks, mask, nr_bits; @@ -299,15 +294,15 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, else ticks = gpmc_ns_to_ticks(time); nr_bits = end_bit - st_bit + 1; - if (ticks >= 1 << nr_bits) { -#ifdef DEBUG - printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n", - cs, name, time, ticks, 1 << nr_bits); -#endif + mask = (1 << nr_bits) - 1; + + if (ticks > mask) { + pr_err("%s: GPMC error! CS%d: %s: %d ns, %d ticks > %d\n", + __func__, cs, name, time, ticks, mask); + return -1; } - mask = (1 << nr_bits) - 1; l = gpmc_cs_read_reg(cs, reg); #ifdef DEBUG printk(KERN_INFO @@ -322,16 +317,10 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, return 0; } -#ifdef DEBUG #define GPMC_SET_ONE(reg, st, end, field) \ if (set_gpmc_timing_reg(cs, (reg), (st), (end), \ t->field, #field) < 0) \ return -1 -#else -#define GPMC_SET_ONE(reg, st, end, field) \ - if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \ - return -1 -#endif int gpmc_calc_divider(unsigned int sync_clk) { From 7604baf365a3bd46007be6fbd2e43ac4a46ce928 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Fri, 29 Aug 2014 19:11:51 +0300 Subject: [PATCH 2/5] ARM: OMAP2+: gpmc: Error out if timings fail in gpmc_probe_generic_child() gpmc_cs_set_timings() returns non-zero if there was an error while setting the GPMC timings. e.g. Timing was too large to be accomodated with current GPMC clock frequency and available timing range. Fail in this case, else we risk operating a NOR device with non compliant timings. Signed-off-by: Roger Quadros Signed-off-by: Sekhar Nori Acked-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 45f680f965ed..f5d9dd256d63 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -1562,7 +1562,12 @@ static int gpmc_probe_generic_child(struct platform_device *pdev, goto err; gpmc_read_timings_dt(child, &gpmc_t); - gpmc_cs_set_timings(cs, &gpmc_t); + ret = gpmc_cs_set_timings(cs, &gpmc_t); + if (ret) { + dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n", + child->name); + goto err; + } no_timings: if (of_platform_device_create(child, NULL, &pdev->dev)) From e378d22b9c27de4af4946e4e7928fef50f9a9ff7 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Fri, 29 Aug 2014 19:11:52 +0300 Subject: [PATCH 3/5] ARM: OMAP2+: gpmc: Always enable A26-A11 for non NAND devices Although RESET state of LIMITEDADDRESS bit in GPMC_CONFIG register is 0 (i.e. A26-A11 enabled), faulty bootloaders might accidentally set this bit. e.g. u-boot 2014.07 with CONFIG_NOR disabled. Explicity disable LIMITEDADDRESS bit for non NAND devices so that they can always work. Signed-off-by: Roger Quadros Signed-off-by: Sekhar Nori Acked-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index f5d9dd256d63..0ba95d3e74e5 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -85,6 +85,8 @@ #define GPMC_ECC_CTRL_ECCREG8 0x008 #define GPMC_ECC_CTRL_ECCREG9 0x009 +#define GPMC_CONFIG_LIMITEDADDRESS BIT(1) + #define GPMC_CONFIG2_CSEXTRADELAY BIT(7) #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7) #define GPMC_CONFIG4_OEEXTRADELAY BIT(7) @@ -1501,6 +1503,7 @@ static int gpmc_probe_generic_child(struct platform_device *pdev, struct resource res; unsigned long base; int ret, cs; + u32 val; if (of_property_read_u32(child, "reg", &cs) < 0) { dev_err(&pdev->dev, "%s has no 'reg' property\n", @@ -1569,6 +1572,11 @@ static int gpmc_probe_generic_child(struct platform_device *pdev, goto err; } + /* Clear limited address i.e. enable A26-A11 */ + val = gpmc_read_reg(GPMC_CONFIG); + val &= ~GPMC_CONFIG_LIMITEDADDRESS; + gpmc_write_reg(GPMC_CONFIG, val); + no_timings: if (of_platform_device_create(child, NULL, &pdev->dev)) return 0; From 4cf27d2ec716fddacd02169af9a26a43ea52875e Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Fri, 29 Aug 2014 19:11:53 +0300 Subject: [PATCH 4/5] ARM: OMAP2+: gpmc: Keep Chip Select disabled while configuring it As per the OMAP reference manual [1], the Chip Select must be disabled (i.e. CSVALID is 0) while configuring any of the Chip select parameters. [1] - 10.1.5.1 Chip-Select Base Address and Region Size Configuration http://www.ti.com/lit/pdf/swpu177 Signed-off-by: Roger Quadros Signed-off-by: Sekhar Nori Acked-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc.c | 34 +++++++++++++++++++++++++++------- 1 file changed, 27 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 0ba95d3e74e5..437fb6f6df52 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -397,7 +397,7 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) return 0; } -static int gpmc_cs_enable_mem(int cs, u32 base, u32 size) +static int gpmc_cs_set_memconf(int cs, u32 base, u32 size) { u32 l; u32 mask; @@ -421,6 +421,15 @@ static int gpmc_cs_enable_mem(int cs, u32 base, u32 size) return 0; } +static void gpmc_cs_enable_mem(int cs) +{ + u32 l; + + l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); + l |= GPMC_CONFIG7_CSVALID; + gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); +} + static void gpmc_cs_disable_mem(int cs) { u32 l; @@ -532,18 +541,18 @@ static int gpmc_cs_remap(int cs, u32 base) gpmc_cs_get_memconf(cs, &old_base, &size); if (base == old_base) return 0; - gpmc_cs_disable_mem(cs); + ret = gpmc_cs_delete_mem(cs); if (ret < 0) return ret; + ret = gpmc_cs_insert_mem(cs, base, size); - if (ret < 0) - return ret; - ret = gpmc_cs_enable_mem(cs, base, size); if (ret < 0) return ret; - return 0; + ret = gpmc_cs_set_memconf(cs, base, size); + + return ret; } int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) @@ -572,12 +581,17 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) if (r < 0) goto out; - r = gpmc_cs_enable_mem(cs, res->start, resource_size(res)); + /* Disable CS while changing base address and size mask */ + gpmc_cs_disable_mem(cs); + + r = gpmc_cs_set_memconf(cs, res->start, resource_size(res)); if (r < 0) { release_resource(res); goto out; } + /* Enable CS */ + gpmc_cs_enable_mem(cs); *base = res->start; gpmc_cs_set_reserved(cs, 1); out: @@ -1539,6 +1553,9 @@ static int gpmc_probe_generic_child(struct platform_device *pdev, goto no_timings; } + /* CS must be disabled while making changes to gpmc configuration */ + gpmc_cs_disable_mem(cs); + /* * FIXME: gpmc_cs_request() will map the CS to an arbitary * location in the gpmc address space. When booting with @@ -1577,6 +1594,9 @@ static int gpmc_probe_generic_child(struct platform_device *pdev, val &= ~GPMC_CONFIG_LIMITEDADDRESS; gpmc_write_reg(GPMC_CONFIG, val); + /* Enable CS region */ + gpmc_cs_enable_mem(cs); + no_timings: if (of_platform_device_create(child, NULL, &pdev->dev)) return 0; From 8bf9be566ed5790003402eb1060184956788b410 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Mon, 1 Sep 2014 15:18:56 +0300 Subject: [PATCH 5/5] ARM: OMAP2+: gpmc: Sanity check GPMC fck on probe This prevents potential division by zero errors if GPMC fck turns out to be zero due to faulty clock data. Use resource managed clk_get() API. Signed-off-by: Roger Quadros Signed-off-by: Sekhar Nori Acked-by: Tony Lindgren --- arch/arm/mach-omap2/gpmc.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 437fb6f6df52..104bc2c50987 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -204,11 +204,6 @@ static unsigned long gpmc_get_fclk_period(void) { unsigned long rate = clk_get_rate(gpmc_l3_clk); - if (rate == 0) { - printk(KERN_WARNING "gpmc_l3_clk not enabled\n"); - return 0; - } - rate /= 1000; rate = 1000000000 / rate; /* In picoseconds */ @@ -1692,13 +1687,18 @@ static int gpmc_probe(struct platform_device *pdev) else gpmc_irq = res->start; - gpmc_l3_clk = clk_get(&pdev->dev, "fck"); + gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck"); if (IS_ERR(gpmc_l3_clk)) { - dev_err(&pdev->dev, "error: clk_get\n"); + dev_err(&pdev->dev, "Failed to get GPMC fck\n"); gpmc_irq = 0; return PTR_ERR(gpmc_l3_clk); } + if (!clk_get_rate(gpmc_l3_clk)) { + dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n"); + return -EINVAL; + } + pm_runtime_enable(&pdev->dev); pm_runtime_get_sync(&pdev->dev); @@ -1741,7 +1741,6 @@ static int gpmc_probe(struct platform_device *pdev) rc = gpmc_probe_dt(pdev); if (rc < 0) { pm_runtime_put_sync(&pdev->dev); - clk_put(gpmc_l3_clk); dev_err(gpmc_dev, "failed to probe DT parameters\n"); return rc; }